EP0092610A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Methods for partitioning mainframe instruction sets to implement microprocessor based emulation thereof
Assignee: International Business Machines Corp
•
Filing: 1982-12-20
•
Granted: —
•
Expires: 2002-12-20
Abstract
Abstract Methods of applying LSI and microprocessors to the design of microprocessor-based LSI implementation of mainframe processors are described. The mainframe instruction set is partitioned into two or more subsets, each of which can be implemented by a microprocessor having special on-chip microcode or by a standard off-the-shelf microprocessor running programs written for that purpose. Alternatively, one or more of the subsets can be implemented by a single microprocessor. In addition, a subset of the partitioned instruction set can be implemented by emulating software, by off-chip vertical or horizontal microcode, or by primitives. But, however partitioning is implemented, the end result thereof is to keep the critical flow paths, associated with the most frequently used instruction subset, as short as possible by constraining them to a single chip.For each subset of the instructions that requires high performance, the corresponding microprocessor chip contains the data flow path and all elements, including registers, necessary for the execution of that subset as well as the microcode that controls execution. In some applications, a subset of the instructions that does not require high performance is implemented with a critical path that crosses several chip boundaries and is, therefore, considerably slower. The application of this method requires partitioning that makes each identified high performance subset executable on one microprocessor in the current state of technology, a way to quickly pass control back and forth between all of the microprocessors, a suitable way to pass data back and forth between all of the microprocessors, and a technology in which it is ecomonically feasible to have several copies of a complex data flow and control store mechanism.
Inventors
- 👤 Anne Sheila Kellerman
- 👤 Raymond Ellison Losinger
- 👤 James William Valashinas
- 👤 Palmer Wright Agnew
- 👤 Joseph Patrick Buonomo
- 👤 Steven Ray Houghtalen
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-28 09:33
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/22; G06F9/223; G06F9/26; G06F9/30; G06F9/3017; G06F9/30174; G06F9/38; G06F9/3877; G06F9/3879
Claims Analysis
Total Claims: 28
Claim 1
Independent Claim
147 words
A method for microprocessor implemented emulation of a mainframe computer, using large scale integrated microprocessor chips, said method comprising the steps of: a) partitioning the instruction set of said mainframe computer into a plurality of subsets, at least one of which completely fits on and is entirely executable by a single microprocessor chip; b) providing chip based microprocessors on which said instruction set subsets can be implemented, each of said microprocessors being capable of supporting on-chip microcode; c) providing each microprocessor with all of the necessary microcode to allow implementation and control execution of its resident subset instructions entirely on-chip; d) providing at least one path between all of said microprocessors via which control can be passed back and forth between said microprocessors; and e) providing at least one path between all of said microprocessors via which data can be passed back and forth between said microprocessors.
Claim 2
Independent Claim
147 words
A method for microprocessor implemented emulation of a mainframe computer, using large scale integrated microprocessor chips, said method comprising the steps of: a) partitioning the instruction set of said mainframe computer into a plurality of subsets, at least one of which completely fits on and is entirely executable by a single microprocessor chip; b) providing chip based microprocessors on which said instruction set subsets can be implemented, each of said microprocessors being capable of supporting on-chip microcode; c) providing each microprocessor with all of the necessary microcode to allow implementation and control execution of its resident subset instructions entirely on-chip; d) providing at least one path between all of said microprocessors via which control can be passed back and forth between said microprocessors; and e) providing at least one path between all of said microprocessors via which data can be passed back and forth between said microprocessors.
Claim 3
Dependent Claim
66 words
The method according to claim 1 wherein said completely fitting instruction subset includes those instructions that make substantial use of the general purpose registers and wherein the microprocessor chip on which said subset is resident is provided with sufficient general purpose registers to handle the instructions of said subset and with microcode for all of the subset's functions that make use of said general purpose registers.
Claim 4
Dependent Claim
65 words
The method according to claim 1 wherein said mainframe instruction set is partitioned into three subsets (P1, Q1 and Rl), and wherein a first and second subset (P1 and Ql) are grouped together for complete implementation on a first single microprocessor chip (A1) and the first and third subset (P1 and Rl) are grouped together for complete implementation on a second single microprocessor chip (Bl).
Claim 5
Dependent Claim
52 words
The method according to claim 3 wherein the first subset (P1) is partitioned to constitute about 95% of the mainframe instruction set by frequency of occurrence and about 70% of the instructions by execution time, with the second and third subset (Ql and Rl) partitioned to include only the remaining mainframe instructions.
Claim 6
Dependent Claim
46 words
The method according to claim 4 wherein the first subset (P1) is partitioned to include only fixed-point, branch and load instructions, the second subset (Q1) is partitioned to include only floating-point instructions and the third subset (Rl) is partitioned to include only decimal and privileged instructions.
Claim 7
Dependent Claim
34 words
The method according to claim 5 wherein said partitioning step is supported by providing on-chip microcode for the first and second microprocessor (A1 and Bl) to implement the respective instruction subset groups of each.
Claim 8
Dependent Claim
26 words
The method according to claim 6 wherein said microprocessors are operated in non-contention with only one being active and the other passive at any one time.
Claim 9
Dependent Claim
113 words
The method according to claim 1 wherein said mainframe instruction set is partitioned into four subsets (P2, Q2, R2 and S2), and which method further includes the steps of providing an off-chip control store and microprocessor chips (A2, B2, C2 and D2), said subsets (P2, Q2 and R2) being each respectively completely implemented on microprocessor chips (A2, B2 and C2), with all remaining mainframe instructions not found in said partitioned subsets (P2, Q2, and R2), namely those contained in one subset (S2), being provided by simulation instruction sequences stored in said off-chip control store, with one microprocessor chip (D2) being used for initialization, program status word (PSW) maintenance, start I/O and housekeeping functions.
Claim 10
Dependent Claim
66 words
The method according to claim 8 wherein one subset ( P 2) is partitioned to implement I-cycles for all instructions and E-cycles for the fixed-point load and branch instructions to gather therein all functions that make frequent use of general purpose registers, another subset (Q2) is partitioned to implement E-cycles for floating-point instructions and a further subset (R2) is partitioned to implement E-cycles for decimal instructions.
Claim 11
Dependent Claim
50 words
The method according to claim 9 wherein said one subset (P2) is partitioned to constitute about 95% of the mainframe instruction set by frequency of occurrence and about 70% of the instructions by execution time, with other subsets (Q2, R2 and S2) partitioned to include only the remaining mainframe instructions.
Claim 12
Dependent Claim
34 words
The method according to claim 10 which further includes the step of providing microcode for each of said microprocessor chips (A2, B2 and C2) to enable full implementation thereon of its assigned instruction subset.
Claim 13
Dependent Claim
113 words
The method according to claim 1 wherein said mainframe instruction set is partitioned into two subsets (P3 and Q3), and which method further includes the steps of providing an off-chip control store and microprocessor chips (A3 and B3), said one (P3) of the subsets being completely implemented on one microprocessor chip (A3), with all remaining mainframe instructions not found in said one partitioned subset (P3), namely those of the other subset (Q3), being provided by simulation instruction sequences stored in said off-chip control store, with the other microprocessor chip (B3) being used for executing said simulation instructions for said other subset (Q3) and also for address translation misses, exception conditions and interrupt handling.
Claim 14
Dependent Claim
41 words
The method according to claim 12 wherein said one subset (P3) is partitioned to implement I-cycles for all instructions and E-cycles for the fixed-point, load and branch instructions to gather therein all functions that make frequent use of general purpose registers.
Claim 15
Dependent Claim
33 words
The method according to claim 13 which further includes the step of providing microcode for said one microprocessor chip (A3) to enable full implementation thereon of its assigned said one instruction subset (P3).
Claim 16
Dependent Claim
48 words
The method according to claim 14 wherein said one subset (P3) is partitioned to constitute about 95% of the mainframe instruction set by frequency of occurrence and about 50% of the instructions by execution time, with said other subset (Q3) partitioned to include only the remaining mainframe instructions.
Claim 17
Dependent Claim
108 words
The method according to claim 1 wherein said mainframe instruction set is partitioned into at least subsets (P4 and Q4), which method further includes the steps of providing a microprocessor chip (A4), implementing one (P4) of the subsets completely on this microprocessor chip (A4) as the machine architecture thereof, and then providing at least one layer of software that will raise the level of said one subset (P4) to that of the full mainframe architecture, said software layer including sufficient instructions and functions to simulate said other instruction subset (Q4), namely the mainframe architecture not defined in and by said one subset (P4), including preservation of system integrity.
Claim 18
Dependent Claim
110 words
The method according to claim 1 wherein said mainframe instruction set is partitioned into two subsets ( P 5 and Q5), and which method further includes the steps of providing an off-chip control store that is suitable for storing vertical microcode therein, providing a microprocessor chip (A5), implementing one subset (P5) completely on said microprocessor chip (A5), with all remaining mainframe instructions not found in said partitioned one subset (P5), namely those of the other subset (Q5), being provided by vertical microcode stored in said off-chip control store, and using said microprocessor chip (A5) for managing said other instruction subset (Q5), and address translation misses, exception conditions and interrupt handling.
Claim 19
Dependent Claim
25 words
The method according to claim 17 wherein said one subset (P5) is partitioned to implement all instructions that do not require infrequently used vertical microcode.
Claim 20
Dependent Claim
32 words
The method according to claim 18 which further includes the step of providing microcode for said microprocessor chip (A5) to enable full implementation thereon of its assigned said one instruction subset (P5).
Claim 21
Dependent Claim
29 words
The method according to claim 19 which includes the additional step of including microcode on said microprocessor chip (A5) to assist in the implementation of said off-chip vertical microcode.
Claim 22
Dependent Claim
39 words
The method according to claim 20 which includes the additional steps of providing a latch coupled to said microprocessor (A5) output pin and branching from on-chip to off-chip vertical microcode by setting said latch whenever a predetermined condition occurs.
Claim 23
Dependent Claim
105 words
The method according to claim 1 wherein said mainframe instruction set is partitioned into two subsets (P6 and Q6), and which method further includes the steps of providng an off-chip control store that is suitable for storing horizontal microcode therein, providing a microprocessor chip (A6), implementing one subset (P6) completely on microprocessor chip (A6), with all remaining mainframe instructions not found in said one partitioned subset (P6), namely those of the other subset (Q6), being provided by horizontal microcode stored in said off-chip control store, and using microprocessor chip (A6) for this and for managing privileged instructions, address translation misses, exception conditions and interrupt handling.
Claim 24
Dependent Claim
25 words
The method according to claim 22 wherein said one subset (P6) is partitioned to implement all instructions that do not require infrequently used horizontal microcode.
Claim 25
Dependent Claim
36 words
The method according to claim 23 which further includes the step of providing microcode for said microprocessor chip ( A 6) to enable full implemen - tation thereon of its assigned said one instruction subset (P6).
Claim 26
Dependent Claim
29 words
The method according to claim 24 which includes the additional step of including microcode on said microprocessor chip (A6) to assist in the implementation of said off-chip horizontal microcode.
Claim 27
Dependent Claim
39 words
The method according to claim 25 which includes the additional steps of providing a latch coupled to the microprocessor (A6) output pin and branching from on-chip to off-chip horizontal microcode by setting said latch whenever a predetermined condition occurs.
Claim 28
Dependent Claim
108 words
The method according to claim 1 wherein said mainframe instruction set is partitioned into two subsets (P7 and Q7), and which method further includes the steps of providing an off-chip control store that is suitable for storing coded therein, providing a microprocessor chip (A7), providing on-chip microcode for implementing said one subset (P7) entirely on said microprocessor (A7), assigning and providing operation codes to identify and implement, as primitives, additional instructions in said one instruction subset (P7) using said on-chip microcode, providing code for said other instruction subset (Q7) that is stored in said off-chip control store and is implemented by a mix of off-chip microcode and primitives.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.