Arithmetic operation processing apparatus of the parallel processing type and compiler which is used in this apparatus

Claim 2

An arithmetic operation processing apparatus of a parallel processing type comprising: a first processor (2) having functions to output a series of macro instruction steps which are obtained by dividing an executing sequence of an instruction to specify arithmetic operating processes to proper executing units and to time-sequentially output a macro instruction to indicate the execution of every macro instruction step divided; a second processor (3) for getting or obtaining said series of macro instruction steps from said first processor (2) and storing and for outputting the instructions included in the relevant macro instruction step in response to the input of said macro instruction; and an arithmetic operating unit (1) for executing an arithmetic operation on the basis of the instruction from said second processor (3).

Claim 3

An apparatus according to Claim 1, wherein said first processor (2) performs the data transfer with said arithmetic operating unit (1) in parallel with the output of the instruction to the arithmetic operating unit (1) from said second processor (3).

Claim 4

An apparatus according to Claim 2, wherein said data transfer is performed between memory means (6) associated with said first processor (2) and a register file (22) which is provided in said arithmetic operating unit (1).

Claim 5

An apparatus according to Claim 3, wherein said first processor (2) can output an instruction for allowing said arithmetic operating unit (1) to execute an arithmetic operation, and said apparatus further has first switching means (11) for receiving both of the instructions from said second (3) and first processors (2) and for selectively connecting either one of said instructions to the arithmetic operating unit (1).

Claim 6

An apparatus according to Claim 2, wherein said second processor (3) has a data input/output function, and said apparatus further has second switching means (13) for selectively connecting either one of said first (2) and second processors (3) to said arithmetic operating unit (1) and for enabling the data transfer to be performed either between the first processor (2) and the arithmetic operating unit (1) or between the second processor (3) and the arithmetic operating unit (1).

Claim 7

An apparatus according to Claim 5, wherein said data transfer between the second processor (3) and the arithmetic operating unit (1) is the data transfer which is performed between a local memory (9) provided in the second processor (3) and a register file (22) provided in the arithmetic operating unit (1).

Claim 8

An apparatus according to Claim 4, wherein said second processor (3) has a data input/output function, and said apparatus further has a second multiplexer (13) for selectively connecting either one of said first and second processors (2, 3) to said arithmetic operating unit (1) and for enabling the data transfer to be executed either between the first processor (2) and the arithmetic operating unit (1) or between the second processor (3) and the arithmetic operating unit (1).

Claim 9

An apparatus according to Claim 1, wherein said first and second processors (2, 3) are made operative by a same machine instruction.

Claim 10

An apparatus according to Claim 1, wherein said macro instruction step is at least one instruction step which is continuously executed.

Claim 11

An apparatus according to Claim 1, wherein the instruction constituting said macro instruction step and said macro instruction are stored as machine language into said first processor (2).

Claim 12

An apparatus according to Claim 1, wherein said first processor (2) has means for indicating the macro instruction representative of the number of instructions to be executed by the arithmetic operating unit (1), and said second processor (3) has means (10) for latching the number of instructions indicated by said second processor (3) and counting the number of arithmetic operating instructions for making the second processor (3) operative each time the instruction is executed by the arithmetic operating unit (1) until the macro instruction coincides with the number of instructions indicated and means for stopping the operation of the first processor (2) until the execution of the macro instruction which is being executed is finished if the next macro instruction is indicated from the first processor (2) while the second processor (3) is operating.

Claim 13

A compiler of a parallel arithmetic operating type for use in an arithmetic operation processing apparatus of a parallel processing type comprising: an arithmetic operation processing unit (1) to perform arithmetic operating processes on the basis of instructions; a second processor (3) having means which divides a whole arithmetic operation processing sequence to be executed by said arithmetic operation processing unit (1) into a plurality of macro sequences and can set these macro sequences as macro instruction steps, and which indicates the instructions one by one on a macro instruc- tion step unit basis to the arithmetic operation processing unit (1) in response to a macro instruction which is input from the outside, and which is returned to a waiting mode of the next macro instruction after completion of the indication of the instructions as many as the relevant macro instruction steps; and a first processor (2) having means for controlling the whole arithmetic operating sequence replaced to a plurality of macro instruction steps and for generating said macro instructions to said second processor (3), said first processor (2) performing a transfer process of necessary data with said arithmetic operation processing unit (1) in parallel with the operations of at least the arithmetic operation processing unit (1) and the second processor (3), wherein said compiler has object program generating means (34) for combining the arithmetic operation processing sequence described as compiling means of a compiler system to describe the arithmetic operation processing sequence of the arithmetic operation processing unit to a plurality of macro sequences consisting of one or more instructions upon compiling along said processing sequence, for defining each of said plurality of macro sequences as a macro instruction step, for assigning said macro instruction steps to the second processor, for assigning the data transfer process and a macro instruction output for the second processor to the first processor (2), and during the execution of the nth macro instruction step by the second processor, for enabling in parallel to therewith data, which will be necessary by the first processor (2) in the (n+l)th and subsequent macro instruc­tion steps, or the resultant data processed by the (n-l)th and preceding macro instruction steps to be transferred between a memory system (6, 22) provided for the first processor and the arithmetic operation processing unit.

Claim 14

A compiler of a parallel arithmetic operating type for use in an arithmetic operation processing apparatus of a parallel processing type comprising: an arithmetic operation processing unit (1) to perform arithmetic operating processes on the basis of instructions; a second processor (3) having means which divides a whole arithmetic operation processing sequence to be executed by said arithmetic operation processing unit (1) into a plurality of macro sequences and can set these macro sequences as macro instruction steps, and which indicates the instructions one by one on a macro instruc- tion step unit basis to the arithmetic operation processing unit (1) in response to a macro instruction which is input from the outside, and which is returned to a waiting mode of the next macro instruction after completion of the indication of the instructions as many as the relevant macro instruction steps; and a first processor (2) having means for controlling the whole arithmetic operating sequence replaced to a plurality of macro instruction steps and for generating said macro instructions to said second processor (3), said first processor (2) performing a transfer process of necessary data with said arithmetic operation processing unit (1) in parallel with the operations of at least the arithmetic operation processing unit (1) and the second processor (3), wherein said compiler has object program generating means (34) for combining the arithmetic operation processing sequence described as compiling means of a compiler system to describe the arithmetic operation processing sequence of the arithmetic operation processing unit to a plurality of macro sequences consisting of one or more instructions upon compiling along said processing sequence, for defining each of said plurality of macro sequences as a macro instruction step, for assigning said macro instruction steps to the second processor, for assigning the data transfer process and a macro instruction output for the second processor to the first processor (2), and during the execution of the nth macro instruction step by the second processor, for enabling in parallel to therewith data, which will be necessary by the first processor (2) in the (n+l)th and subsequent macro instruc­tion steps, or the resultant data processed by the (n-l)th and preceding macro instruction steps to be transferred between a memory system (6, 22) provided for the first processor and the arithmetic operation processing unit.

Claim 15

A compiler according to Claim 12, wherein as means for compiling loop arithmetic operations, there is further used a compiling system which develops loop processes to object programs in a manner such that the series of arithmetic operating processes in the loop are regarded as the macro sequences and defined to the macro instruction steps and assigned to the second processor (3), the data transfer processing and the generating operation of the macro instruction to the second processor (3) are assigned to the first processor, and during the execution of the macro instruction step of the nth loop by the first processor (2), there is executed in parallel therewith the process to transfer data, which will be necessary by the first processor (2) in the macro instruction steps of the (n+l)th and subsequent loops, or the resultant data processed by the (n-l)th and preceding macro instruction steps between the memory system (6, 22) provided for the first processor (2) and the arithmetic operation processing unit (1).