Patent US5956582A successfully refreshed from Google Patents.
US5956582A
Expired / Lapsed
US
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Current limiting circuit with continuous metallization
Assignee: STMicroelectronics SA
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Filing: 1997-06-13
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Granted: 1999-09-21
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Expires: 2017-06-13
Abstract
Abstract A two-terminal current limiting component, includes a substrate of a first conductivity type; separated wells of the second conductivity type; a first annular region of the first conductivity type in each well; a second annular region of the first conductivity type having a low doping level between the periphery of each first annular region and the periphery of each well; an insulating layer over the second annular region and the surface portions of the substrate; a first metallization coating the upper surface of the component; and a second metallization coating the lower surface of the component.
Inventors
- 👤 Christophe Ayela
- 👤 Philippe Leturcq
- 👤 Jean Jalade
- 👤 Jean-Louis Sanchez
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 15:55
CPC Classifications
H; H10; H10D; H10D89/00; H10D89/60; H10D89/601; H02; H02H; H02H9/00; H02H9/02; H02H9/025; H10D1/00; H10D1/40; Y; Y10; Y10S; Y10S438/00; Y10S438/942
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
173 words
A method for manufacturing a two-terminal component in a substrate of the first conductivity type, including the following steps: forming, through a first mask, wells of the second conductivity type having walls therebetween; forming, in each of said wells, by using the first mask and an additional mask, annular regions of the second conductivity type; implanting a dopant of the first conductivity type by using a third mask that does not cover a peripheral portion of each of the wells between an outer portion and the annular region, to invert the conductivity type of said peripheral region; growing an oxide layer having a predetermined thickness for gate insulation; etching the oxide layers over a central portion of each of the wells, including an inner portion of each annular region; forming a continuous metallization to form both an oxide-isolated gate over the oxide layer and a source contact over the central portions of each well, the gate and the source held thereby at substantially equal voltages; and forming a metallization on the rear surface.
Claim 2
Independent Claim
173 words
A method for manufacturing a two-terminal component in a substrate of the first conductivity type, including the following steps: forming, through a first mask, wells of the second conductivity type having walls therebetween; forming, in each of said wells, by using the first mask and an additional mask, annular regions of the second conductivity type; implanting a dopant of the first conductivity type by using a third mask that does not cover a peripheral portion of each of the wells between an outer portion and the annular region, to invert the conductivity type of said peripheral region; growing an oxide layer having a predetermined thickness for gate insulation; etching the oxide layers over a central portion of each of the wells, including an inner portion of each annular region; forming a continuous metallization to form both an oxide-isolated gate over the oxide layer and a source contact over the central portions of each well, the gate and the source held thereby at substantially equal voltages; and forming a metallization on the rear surface.
Claim 3
Dependent Claim
24 words
The method of claim 1, wherein said third mask includes portions for protecting intermediate areas of the substrate between adjacent walls between the wells.
Claim 4
Dependent Claim
55 words
The method of claim 1, wherein the doping level of the dopant of the first conductivity type is selected so that a limitation current defined by the component has a value that is substantially constant when temperature varies, while a channel length is selected so as to obtain a desired value for the limitation current.
Claim 5
Independent Claim
106 words
A method of fabricating a two-terminal component constituting a depletion type MOS or IGBT transistor of a vertical double-diffused type wherein a source and a gate of the transistor are made of a single continuous metallization which holds the gate and the source at substantially equal voltages, and wherein a depleted channel region results from an implantation of a first conductivity type formed in a peripheral region of a second conductivity type, so that a doping level of the depleted channel region of the first conductivity type is such that a limitation current of the component has a value that is substantially constant when temperature varies.
Claim 6
Independent Claim
106 words
A method of fabricating a two-terminal component constituting a depletion type MOS or IGBT transistor of a vertical double-diffused type wherein a source and a gate of the transistor are made of a single continuous metallization which holds the gate and the source at substantially equal voltages, and wherein a depleted channel region results from an implantation of a first conductivity type formed in a peripheral region of a second conductivity type, so that a doping level of the depleted channel region of the first conductivity type is such that a limitation current of the component has a value that is substantially constant when temperature varies.
Claim 7
Dependent Claim
26 words
The method of claim 4, wherein a length of the depleted channel region is selected so as to obtain a desired value for the limitation current.
Claim 8
Dependent Claim
176 words
A method for manufacturing a two-terminal component according to claim 5, in a substrate of the first conductivity type, including the following steps: forming, through a first mask, wells of the second conductivity type having walls therebetween; forming, in each of said wells, by using the first mask and an additional mask, annular regions of the second conductivity type; implanting a dopant of the first conductivity type by using a third mask that does not cover a peripheral portion of each of the wells between an outer portion and the annular region, to invert the conductivity type of said peripheral region; growing an oxide layer having a predetermined thickness for gate insulation; etching the oxide layer over a central portion of each of the wells, including an inner portion of each annular region; forming a continuous metallization to form both an oxide-isolated gate over the oxide layer and a source contact over the central portions of each well the gate and source held thereby at substantially equal voltages; and forming a metallization on the rear surface.
Claim 9
Dependent Claim
24 words
The method of claim 6, wherein said third mask includes portions for protecting intermediate areas of the substrate between adjacent walls between the wells.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-09-20 | 2003-03-22 | 2003-09-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-09-20 | 2007-03-22 | 2007-09-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-09-20 | 2011-03-22 | 2011-09-21 | $7700.00 | Window Closed / Lapsed |