US5956522A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Symmetric multiprocessing system with unified environment and distributed system functions
Assignee: RPX Corp
•
Filing: 1995-03-16
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Granted: 1999-09-21
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Expires: 2015-03-16
Abstract
Abstract A symmetric multiprocessing system with a unified environment and distributed system functions provides unified address space for all functional units in the system while distributing the execution of various system functions over the functional units of the system whereby each functional unit assumes responsibility for its own aspects of these operations. In addition, the system provides improved system bus operation for transfer of data from memory.
Inventors
- 👤 James F. Bertone
- 👤 Bruno DiPlacido, Jr.
- 👤 Thomas F Joyce
- 👤 Martin Massucci
- 👤 Lance T. McNally
- 👤 Thomas L. Murray, Jr.
- 👤 Chester M. Nibby, Jr.
- 👤 Michelle A. Pence
- 👤 Marc Sanfacon
- 👤 Jian-Kuo Shen
- 👤 Jeffrey S. Somers
- 👤 G. Lewis Steiner
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 09:34
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F13/16; G06F13/1605; G06F13/1652; G06F13/1657; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0806; G06F12/0815; G06F12/0831; G06F13/1668; G06F13/1689; G06F13/1694; G06F13/36; G06F13/368
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
130 words
An input and output bridge connected between a system bus, connected to a shared memory, and at least one peripheral device for performing direct memory accesses, comprising: a cache memory; and a cache prefetch controller responsive to a request for a direct memory access operation said cache prefetch controller including means for ceasing to respond to cache operations issued over the system bus, means for clearing the cache memory, means for controlling the cache memory to operate as a buffer for a direct memory access operation, means for detecting a system bus read or write request cache hit for any byte in a bus double word, and means for performing a corresponding cache line invalidate or prefetch operation on a word boundary of a word including the cache hit byte.
Claim 2
Dependent Claim
130 words
An input and output bridge connected between a system bus, connected to a shared memory, and at least one peripheral device for performing direct memory accesses, comprising: a cache memory; and a cache prefetch controller responsive to a request for a direct memory access operation said cache prefetch controller including means for ceasing to respond to cache operations issued over the system bus, means for clearing the cache memory, means for controlling the cache memory to operate as a buffer for a direct memory access operation, means for detecting a system bus read or write request cache hit for any byte in a bus double word, and means for performing a corresponding cache line invalidate or prefetch operation on a word boundary of a word including the cache hit byte.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-09-20 | 2003-03-22 | 2003-09-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-09-20 | 2007-03-22 | 2007-09-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-09-20 | 2011-03-22 | 2011-09-21 | $7700.00 | Window Closed / Lapsed |