Frequency multiplier using a voltage controlled delay circuit

Claim 2

A frequency multiplying circuit for multiplying a frequency of a reference signal by N, N being an integer greater than one, comprising: a voltage controlled delay circuit for receiving the reference signal at an input terminal and generating a delay signal at an output terminal, said voltage controlled delay circuit having a control voltage input terminal, and 2N intermediate terminals for outputting respective intermediate signals delayed by, respectively, 1/2N, 2/2N, 3/2N, . . . , 2N/2N times a delay which the delay signal has with respect to the reference signal; a phase comparator supplied, at a first input terminal, with the delay signal output from the voltage controlled delay circuit and, at a second terminal, with the reference signal to produce an error signal corresponding to a phase difference between the delay signal and the reference signal; a low pass filter supplied, at an input terminal, with the error signal from the phase comparator and having an output terminal connected to the control voltage input terminal of the voltage controlled delay circuit; an N multiplying logic circuit having 2N input terminals connected to the intermediate terminals, respectively, for logically combining consecutive pairs of said intermediate signals to produce N respective output pulses for each period of said reference signal at N intermediate output terminals, wherein rising and falling edges of each of the N respective output pulses are both always triggered only by leading edges of said intermediate signals; and an adder coupled to said N intermediate output terminals and configured to combine said N respective output pulses to produce an N multiplied signal.

Claim 3

A frequency multiplying circuit according to claim 1, wherein the N multiplying logic circuit comprises: an N number of flip flop circuits having input terminals connected to the input terminals of N multiplying logic circuit.

Claim 4

A frequency multiplying circuit for multiplying a frequency of a reference signal by N, N being an integer greater than one, compising: a voltage controlled delay circuit for receiving the reference signal at an input terminal and generating a delay signal at at output terminal, said voltage controlled delay circuit having a control voltage input terminal, and N intermediate terminals for outputting respective intermediate signals delayed by, respectively, 1/N, 2/N, 3/N, . . . N/N times a delay which the delay signal has with respect to the reference signal; a phase comparator supplied, at a first input terminal, with an inverted replica of the delay signal output from the voltage controlled delay circuit and, at a second input terminal, with the reference signal to produce an error signal corresponding to a phase difference between the delay signal and the reference signal; a low pass filter supplied, at an input terminal, with the error signal from the phase comparator and having an output terminal connected to the control voltage input terminal of the voltage controlled delay circuit; an N multiplying logic circuit having 2N input terminals, N input terminals being connected to the N intermediate terminals respectively and the remaining N input terminals being supplied with inverted replicas of signal outputs from the N intermediate terminals, for logically combining consecutive pairs of said intermediate signals and said inverted replicas of said intermediate signals to produce N respective output pulses for each period of said reference signal at N intermediate output terminals, wherein rising and falling edges of each of the N respective output pulses are both always triggered only by leading edges of said intermediate signals and by leading edges of said inverted replicas of said intermediate signals; and an adder coupled to said N intermediate out terminals and configured to combine said N respective output pulses to produce an N multiplied signal.

Claim 5

A frequency multiplying circuit for multiplying a frequency of a reference signal by N, N being an integer greater than one, compising: a voltage controlled delay circuit for receiving the reference signal at an input terminal and generating a delay signal at at output terminal, said voltage controlled delay circuit having a control voltage input terminal, and N intermediate terminals for outputting respective intermediate signals delayed by, respectively, 1/N, 2/N, 3/N, . . . N/N times a delay which the delay signal has with respect to the reference signal; a phase comparator supplied, at a first input terminal, with an inverted replica of the delay signal output from the voltage controlled delay circuit and, at a second input terminal, with the reference signal to produce an error signal corresponding to a phase difference between the delay signal and the reference signal; a low pass filter supplied, at an input terminal, with the error signal from the phase comparator and having an output terminal connected to the control voltage input terminal of the voltage controlled delay circuit; an N multiplying logic circuit having 2N input terminals, N input terminals being connected to the N intermediate terminals respectively and the remaining N input terminals being supplied with inverted replicas of signal outputs from the N intermediate terminals, for logically combining consecutive pairs of said intermediate signals and said inverted replicas of said intermediate signals to produce N respective output pulses for each period of said reference signal at N intermediate output terminals, wherein rising and falling edges of each of the N respective output pulses are both always triggered only by leading edges of said intermediate signals and by leading edges of said inverted replicas of said intermediate signals; and an adder coupled to said N intermediate out terminals and configured to combine said N respective output pulses to produce an N multiplied signal.

Claim 6

A frequency multiplying circuit according to claim 3, wherein the N multiplying logic circuit comprises: an N number of flip flop circuits having input terminals connected to the input terminals of N multiplying logic circuit.

Claim 7

A frequency multiplying circuit for multiplying a frequency of a reference signal by N, N being an integer greater than one, comprising: a voltage controlled delay circuit for receiving the reference signal at an input terminal and generating a delay signal at an output terminal, said voltage controlled delay circuit having a control voltage input terminal, and 2N intermediate terminals for outputting respective intermediate signals delayed by, respectively, 1/2N, 2/2N, 3/2N, . . . 2N/2N times a delay which the delay signal has with respect to the reference signal; an N multiplying logic circuit having 2N input terminals connected to the intermediate terminals, respectively, for logically combining consecutive pairs of said intermediate signals to produce N respective output pulses for each period of said reference signal at N intermediate output terminals, wherein rising and falling edges of each of the N respective output pulsed are both always triggered only by leading edges of said intermediate signals and by leading edges of said inverted replicas of said intermediate signals, an adder coupled to said N intermediate output terminals and configured to combine said N respective output pusles to produce an N multiplied output signal; a divide-by-N frequency divider supplied, at an input terminal, with the N multiplied output signal from the N multiplying logic circuit and producing an N divided output signal; phase comparator supplied, at a first input terminal, with the N divided output signal from the divide-by-N frequency divider and, at a second input terminal, with the reference signal to produce an error signal corresponding to a phase difference between both the signals; and a low pass filter supplied, at an input terminal, with the error signal from the phase comparator and having an output terminal connected to the control voltage input terminal of the voltage controlled delay circuit.

Claim 8

A frequency multiplying circuit for multiplying a frequency of a reference signal by N, N being an integer greater than one, comprising: a voltage controlled delay circuit for receiving the reference signal at an input terminal and generating a delay signal at an output terminal, said voltage controlled delay circuit having a control voltage input terminal, and 2N intermediate terminals for outputting respective intermediate signals delayed by, respectively, 1/2N, 2/2N, 3/2N, . . . 2N/2N times a delay which the delay signal has with respect to the reference signal; an N multiplying logic circuit having 2N input terminals connected to the intermediate terminals, respectively, for logically combining consecutive pairs of said intermediate signals to produce N respective output pulses for each period of said reference signal at N intermediate output terminals, wherein rising and falling edges of each of the N respective output pulsed are both always triggered only by leading edges of said intermediate signals and by leading edges of said inverted replicas of said intermediate signals, an adder coupled to said N intermediate output terminals and configured to combine said N respective output pusles to produce an N multiplied output signal; a divide-by-N frequency divider supplied, at an input terminal, with the N multiplied output signal from the N multiplying logic circuit and producing an N divided output signal; phase comparator supplied, at a first input terminal, with the N divided output signal from the divide-by-N frequency divider and, at a second input terminal, with the reference signal to produce an error signal corresponding to a phase difference between both the signals; and a low pass filter supplied, at an input terminal, with the error signal from the phase comparator and having an output terminal connected to the control voltage input terminal of the voltage controlled delay circuit.

Claim 9

A frequency multiplying circuit according to claim 5, wherein the N multiplying logic circuit comprises: an N number of flip flop circuits having input terminals connected to the input terminals of N multiplying logic circuit.

Claim 10

A frequency multiplying circuit for multiplying a frequency of a reference signal by N, N being an integer greater than one, comprising: a voltage controlled delay circuit for receiving the reference signal at an input terminal and generating a delay signal at an output terminal, said voltage controlled delay circuit having a control voltage input terminal, and 2N intermediate terminals for outputting signals delayed by, respectively, 1/2N, 2/2N, 3/2N, . . . 2N/2N times a delay which the delay signal has with respect to the reference signal; an N multiplying logic circuit having 2N input terminals connected to the intermediate terminals, respectively, for logically combining consecutive pairs of said intermediate signals to produce N respective output pulses for each period of said reference signal at N intermediate output terminals, wherein rising and falling edges of each of the N respective output pulses are both always triggered only by leading edges of said intermediate signals; an adder coupled to said N intermediate output terminals and continued to combine said N respective output pulses to produce an N multiplied output signal; a synchronous circuit supplied, at a data input terminal, with the delay signal from the voltage controlled delay circuit and, at a clock input terminal, with the N multiplied output signal from the N multiplying logic circuit to produce a delay signal corresponding to the output signal; a phase comparator connected at a first input terminal to an output terminal of the synchronous circuit and supplied, at a second input terminal, with the reference signal to produce an error signal corresponding to a phase difference between both the signals; and a low pass filter supplied, at an input terminal, with the error signal from the phase comparator and having an output terminal connected to the control voltage input terminal of the voltage controlled delay circuit.

Claim 11

A frequency multiplying circuit for multiplying a frequency of a reference signal by N, N being an integer greater than one, comprising: a voltage controlled delay circuit for receiving the reference signal at an input terminal and generating a delay signal at an output terminal, said voltage controlled delay circuit having a control voltage input terminal, and 2N intermediate terminals for outputting signals delayed by, respectively, 1/2N, 2/2N, 3/2N, . . . 2N/2N times a delay which the delay signal has with respect to the reference signal; an N multiplying logic circuit having 2N input terminals connected to the intermediate terminals, respectively, for logically combining consecutive pairs of said intermediate signals to produce N respective output pulses for each period of said reference signal at N intermediate output terminals, wherein rising and falling edges of each of the N respective output pulses are both always triggered only by leading edges of said intermediate signals; an adder coupled to said N intermediate output terminals and continued to combine said N respective output pulses to produce an N multiplied output signal; a synchronous circuit supplied, at a data input terminal, with the delay signal from the voltage controlled delay circuit and, at a clock input terminal, with the N multiplied output signal from the N multiplying logic circuit to produce a delay signal corresponding to the output signal; a phase comparator connected at a first input terminal to an output terminal of the synchronous circuit and supplied, at a second input terminal, with the reference signal to produce an error signal corresponding to a phase difference between both the signals; and a low pass filter supplied, at an input terminal, with the error signal from the phase comparator and having an output terminal connected to the control voltage input terminal of the voltage controlled delay circuit.

Claim 12

A frequency multiplying circuit according to claim 7, wherein the N multiplying logic circuit comprises: an N number of flip flop circuits having input terminals connected to the input terminals of N multiplying logic circuit.

Claim 13

A frequency multiplying circuit for multiplying a frequency of an oscillation signal by N, N being an integer greater than one, comprising: a voltage controlled oscillator having an input terminal connected to an output terminal thereof and supplying the oscillation signal at the output terminal, said voltage controlled oscillator having N intermediate terminals for outputting respective intermediate signals delayed by, respectively, 1/2N, 2/2N, 3/2N, . . . N/2N times a period of the oscillation signal; a frequency divider connected at an input terminal to the output terminal of the voltage controlled oscillator to generate a frequency divided signal from the oscillation signal; a phase comparator supplied at a first input terminal with the frequency divided signal from the frequency divider and at a second input terminal with a reference signal to generate an error signal corresponding to a phase difference between both the signals; a lowpass filter supplied at an input terminal with the error signal from the phase comparator and connected at an output terminal to a control voltage input terminal of the voltage controlled oscillator; N exclusive OR circuits each connected at a first input terminal with an output terminal of the voltage controlled oscillator and at a second input terminal to the N intermediate terminals of the voltage con d oscillator, respectively and producing N intermediate signals at respective output terminal of said N exclusive OR circuits; and an N multiplying logic circuit having N input terminals connected to the output terminals of the N exclusive OR circuits, respectively, for logically combining consecutive pairs of said intermediate signals to produce N respective output pulses for each period of said reference signal at N intermediate output terminals, wherein rising and falling edges of each of the N respective output pulses are both always triggered only by leading edges of said intermediate signals; and an adder coupled to said N intermediate output terminals and configured to combine said N respective output pulses to produce N multiplied output signal.

Claim 14

A frequency multiplying circuit for multiplying a frequency of an oscillation signal by N, N being an integer greater than one, comprising: a voltage controlled oscillator having an input terminal connected to an output terminal thereof and supplying the oscillation signal at the output terminal, said voltage controlled oscillator having N intermediate terminals for outputting respective intermediate signals delayed by, respectively, 1/2N, 2/2N, 3/2N, . . . N/2N times a period of the oscillation signal; a frequency divider connected at an input terminal to the output terminal of the voltage controlled oscillator to generate a frequency divided signal from the oscillation signal; a phase comparator supplied at a first input terminal with the frequency divided signal from the frequency divider and at a second input terminal with a reference signal to generate an error signal corresponding to a phase difference between both the signals; a lowpass filter supplied at an input terminal with the error signal from the phase comparator and connected at an output terminal to a control voltage input terminal of the voltage controlled oscillator; N exclusive OR circuits each connected at a first input terminal with an output terminal of the voltage controlled oscillator and at a second input terminal to the N intermediate terminals of the voltage con d oscillator, respectively and producing N intermediate signals at respective output terminal of said N exclusive OR circuits; and an N multiplying logic circuit having N input terminals connected to the output terminals of the N exclusive OR circuits, respectively, for logically combining consecutive pairs of said intermediate signals to produce N respective output pulses for each period of said reference signal at N intermediate output terminals, wherein rising and falling edges of each of the N respective output pulses are both always triggered only by leading edges of said intermediate signals; and an adder coupled to said N intermediate output terminals and configured to combine said N respective output pulses to produce N multiplied output signal.

Claim 15

A frequency multiplying circuit according to claim 9, wherein the N multiplying logic circuit comprises: an N number of flip flop circuits having input terminals connected to the input terminals of N multiplying logic circuit.

Claim 16

A frequency multiplying circuit for multiplying a frequency of an oscillation signal by N, N being am integer greater than one, compising: a voltage controlled oscillator having an input terminal connected to an output terminal thereof and supplying the oscillation signal at the output terminal, said voltage controlled oscillator having N intermediate terminals for outputting signals delayed by, respectively, 1/2N, 2/2N, 3/2N, . . . N/2N times a period of the oscillation signal; a voltage controlled delay circuit connected at an input terminal to the output terminal of the voltage controlled oscillator and having N intermediate terminals for outputting signals delayed by, respectively, N+1/2N, N+2/2N, N+3/2N, . . . 2N/2N times a period of the oscillation signal; a frequency divider connected at an input terminal to the output terminal of the voltage controlled oscillator to produce a frequency divided signal from the oscillation signal; a phase comparator supplied, at a first input terminal, with the frequency divided signal from the frequency divider and, at a second input terminal, with a reference signal to produce an error signal corresponding to a phase difference between both the signals; a low pass filter supplied, at an input terminal, with the error signal and connected at an output terminal to a control voltage input terminal of the voltage controlled oscillator and to a control voltage input terminal of the voltage controlled delay circuit; an N multiplying logic circuit having 2N input terminals, N input terminals of which are connected to the N intermediate terminals of the voltage controlled oscillator and the remaining N input terminals of which are connected to the N intermediate terminals of the voltage controlled delay circuit, respectively, for logically combining consecutive pairs of said intermediate signals to produce N respective output pulses for each period of said reference signal at N intermediate output terminals, wherein rising and falling edges of each of the N respective output pulses are both always triggered only by leading edges of said intermediate signals; and an adder coupled to said N intermediate output terminals and configured to combine said N respective output pulses to produce an N multiplied output signal.

Claim 17

A frequency multiplying circuit for multiplying a frequency of an oscillation signal by N, N being am integer greater than one, compising: a voltage controlled oscillator having an input terminal connected to an output terminal thereof and supplying the oscillation signal at the output terminal, said voltage controlled oscillator having N intermediate terminals for outputting signals delayed by, respectively, 1/2N, 2/2N, 3/2N, . . . N/2N times a period of the oscillation signal; a voltage controlled delay circuit connected at an input terminal to the output terminal of the voltage controlled oscillator and having N intermediate terminals for outputting signals delayed by, respectively, N+1/2N, N+2/2N, N+3/2N, . . . 2N/2N times a period of the oscillation signal; a frequency divider connected at an input terminal to the output terminal of the voltage controlled oscillator to produce a frequency divided signal from the oscillation signal; a phase comparator supplied, at a first input terminal, with the frequency divided signal from the frequency divider and, at a second input terminal, with a reference signal to produce an error signal corresponding to a phase difference between both the signals; a low pass filter supplied, at an input terminal, with the error signal and connected at an output terminal to a control voltage input terminal of the voltage controlled oscillator and to a control voltage input terminal of the voltage controlled delay circuit; an N multiplying logic circuit having 2N input terminals, N input terminals of which are connected to the N intermediate terminals of the voltage controlled oscillator and the remaining N input terminals of which are connected to the N intermediate terminals of the voltage controlled delay circuit, respectively, for logically combining consecutive pairs of said intermediate signals to produce N respective output pulses for each period of said reference signal at N intermediate output terminals, wherein rising and falling edges of each of the N respective output pulses are both always triggered only by leading edges of said intermediate signals; and an adder coupled to said N intermediate output terminals and configured to combine said N respective output pulses to produce an N multiplied output signal.

Claim 18

A frequency multiplying circuit according to claim 11, wherein the N multiplying logic circuit comprises: an N number of flip flop circuits having input terminals connected to the input terminals of N multiplying logic circuit.

Claim 19

A frequency multiplying circuit for multiplying a frequency of a reference signal by N, N being an integer greater than one, comprising: a voltage controlled delay circuit for receiving the reference signal at an input terminal and generating a delay signal at an output terminal, said voltage controlled delay circuit having a control voltage input terminal, ad 2N intermediate terminals for outputting respective intermediate signals delayed by, respectively, 1/2N, 2/2N, 3/2N, . . . 2N/2N times a delay which the delay signal has with respect to the reference signal; a phase comparator supplied, at a first input terminal, with the delay signal output from the voltage controlled delay circuit and, at a second terminal, with the reference signal to produce an error signal corresponding to a phase difference between the delay signal and the reference signal; a low pass filter supplied, at an input terminal, with the error signal from the phase comparator and having an output terminal connected to the control voltage input terminal of the voltage controlled delay circuit; an N multiplying logic circuit having 2N input terminals connected to the intermediate terminals, respectively, for logically combining consecutive pairs of said intermediate signals to produce N respective output pulses for each period of said reference signal at N intermediate output terminals, wherein rising and falling edges of each of the N respective output pulses are both always triggered only by trailing edges of said intermediate signals; and an adder coupled to said N intermediate output terminals and configured to combine said N respective output pulses to produce an N multiplied output signal.

Claim 20

A frequency multiplying circuit for multiplying a frequency of a reference signal by N, N being an integer greater than one, comprising: a voltage controlled delay circuit for receiving the reference signal at an input terminal and generating a delay signal at an output terminal, said voltage controlled delay circuit having a control voltage input terminal, ad 2N intermediate terminals for outputting respective intermediate signals delayed by, respectively, 1/2N, 2/2N, 3/2N, . . . 2N/2N times a delay which the delay signal has with respect to the reference signal; a phase comparator supplied, at a first input terminal, with the delay signal output from the voltage controlled delay circuit and, at a second terminal, with the reference signal to produce an error signal corresponding to a phase difference between the delay signal and the reference signal; a low pass filter supplied, at an input terminal, with the error signal from the phase comparator and having an output terminal connected to the control voltage input terminal of the voltage controlled delay circuit; an N multiplying logic circuit having 2N input terminals connected to the intermediate terminals, respectively, for logically combining consecutive pairs of said intermediate signals to produce N respective output pulses for each period of said reference signal at N intermediate output terminals, wherein rising and falling edges of each of the N respective output pulses are both always triggered only by trailing edges of said intermediate signals; and an adder coupled to said N intermediate output terminals and configured to combine said N respective output pulses to produce an N multiplied output signal.

Claim 21

A frequency multiplying circuit according to claim 13, wherein the N multiplying logic circuit comprises: an N number of flip-flop circuits having input terminals connected to the input terminals of the N multiplying logical circuit.

Claim 22

A frequency multiplying circuit for multiplying a frequency of a reference signal by N, N being an integer greater than one, comprising: a voltage controlled delay circuit for receiving the reference signal at an input terminal and generating a delay signal at an output terminal, said voltage controlled delay circuit having a control voltage input terminal, and N intermediate terminals for outputting respective intermediate signals delayed by, respectively, 1/N, 2/N, 3/N, . . . N/N times a delay which the delay signal has with respect to the reference signal; a phase comparator supplied, at a first input terminal, with an inverted replica of the delay signal output from the voltage controlled delay circuit and, at a second input terminal, with the reference signal to produce an error signal corresponding to a phase difference between the delay signal and the reference signal; a low pass filter supplied, at an input terminal, with the error signal from the phase comparator and having an output terminal connected to the control voltage input terminal of the voltage controlled delay circuit; an N multiplying logic circuit having 2N input terminals, N input terminals being connected to the N intermediate terminals respectively and the remaining N input terminals being supplied with inverted replicas of signal outputs from the N intermediate terminals, for logically combining consecutive pairs of said intermediate signals and said inverted replicas of said intermediate signals to produce N respective output pulses for each period of said reference signal at N intermediate output terminals, wherein rising and failing edges of each of the N respective output pulses are both always triggered only by trailing edges of said intermediate signals and by trailing edges of said inverted replicas of said intermediate signals; and an adder coupled to said N intermediate output terminals and configured to combine said N respective output pulses to produce an N multiplied output signal.

Claim 23

A frequency multiplying circuit for multiplying a frequency of a reference signal by N, N being an integer greater than one, comprising: a voltage controlled delay circuit for receiving the reference signal at an input terminal and generating a delay signal at an output terminal, said voltage controlled delay circuit having a control voltage input terminal, and N intermediate terminals for outputting respective intermediate signals delayed by, respectively, 1/N, 2/N, 3/N, . . . N/N times a delay which the delay signal has with respect to the reference signal; a phase comparator supplied, at a first input terminal, with an inverted replica of the delay signal output from the voltage controlled delay circuit and, at a second input terminal, with the reference signal to produce an error signal corresponding to a phase difference between the delay signal and the reference signal; a low pass filter supplied, at an input terminal, with the error signal from the phase comparator and having an output terminal connected to the control voltage input terminal of the voltage controlled delay circuit; an N multiplying logic circuit having 2N input terminals, N input terminals being connected to the N intermediate terminals respectively and the remaining N input terminals being supplied with inverted replicas of signal outputs from the N intermediate terminals, for logically combining consecutive pairs of said intermediate signals and said inverted replicas of said intermediate signals to produce N respective output pulses for each period of said reference signal at N intermediate output terminals, wherein rising and failing edges of each of the N respective output pulses are both always triggered only by trailing edges of said intermediate signals and by trailing edges of said inverted replicas of said intermediate signals; and an adder coupled to said N intermediate output terminals and configured to combine said N respective output pulses to produce an N multiplied output signal.

Claim 24

The frequency multiplying circuit according to claim 15, wherein the N multiplying logic circuit comprises an N number of flip-flop circuits having input terminals connected to the input terminals of the N multiplying logic circuit.

Claim 25

A frequency multiplying circuit for multiplying a frequency of a reference signal by N, N being an integer greater than one, comprising: a voltage controlled delay circuit for receiving the reference signal at an input terminal and generating a delay signal at an output terminal, said voltage controlled delay circuit having a control voltage input terminal, and 2N intermediate terminals for outputting respective intermediate signals delayed by, respectively, 1/2N, 2/2N, 3/2N, . . . 2N/2N times a delay which the delay signal has with respect to the reference signal; an N multiplying logic circuit having 2N input terminals connected to the intermediate terminals, respectively, for logically combining consecutive pairs of said intermediate signals to produce N respective output pulses for each period of said reference signal at N intermediate output terminals, wherein rising and falling edges of each of the N respective output pulses are both always triggered only by trailing edges of said intermediate signals and by trailing edges of said inverted replicas of said intermediate signals; an adder coupled to said N intermediate output terminals and configured to combine said N respective output pulses to produce an N multiplied output signal; a divide-by-N frequency divider supplied, at an input terminal, with the N multiplied output signal from the N multiplying logic circuit and producing an N divided output signal; a phase comparator supplied, at a first input terminal, with the N divided output signal from the divide-by-N frequency divider and, at a second input terminal, with the reference signal to produce an error signal corresponding to a phase difference between both the signals; and a low pass filter supplied, at an input terminal, with the error signal from the phase comparator and having an output terminal connected to the control voltage input terminal of the voltage controlled delay circuit.

Claim 26

A frequency multiplying circuit for multiplying a frequency of a reference signal by N, N being an integer greater than one, comprising: a voltage controlled delay circuit for receiving the reference signal at an input terminal and generating a delay signal at an output terminal, said voltage controlled delay circuit having a control voltage input terminal, and 2N intermediate terminals for outputting respective intermediate signals delayed by, respectively, 1/2N, 2/2N, 3/2N, . . . 2N/2N times a delay which the delay signal has with respect to the reference signal; an N multiplying logic circuit having 2N input terminals connected to the intermediate terminals, respectively, for logically combining consecutive pairs of said intermediate signals to produce N respective output pulses for each period of said reference signal at N intermediate output terminals, wherein rising and falling edges of each of the N respective output pulses are both always triggered only by trailing edges of said intermediate signals and by trailing edges of said inverted replicas of said intermediate signals; an adder coupled to said N intermediate output terminals and configured to combine said N respective output pulses to produce an N multiplied output signal; a divide-by-N frequency divider supplied, at an input terminal, with the N multiplied output signal from the N multiplying logic circuit and producing an N divided output signal; a phase comparator supplied, at a first input terminal, with the N divided output signal from the divide-by-N frequency divider and, at a second input terminal, with the reference signal to produce an error signal corresponding to a phase difference between both the signals; and a low pass filter supplied, at an input terminal, with the error signal from the phase comparator and having an output terminal connected to the control voltage input terminal of the voltage controlled delay circuit.

Claim 27

A frequency multi lying circuit according to claim 17, wherein the N multiplying logic circuit comprises an N number of flip-flop circuits connected at input terminals to input terminals of the N multiplying logic circuit.

Claim 28

A frequency multiplying circuit for multiplying a frequency of a reference signal by N, N being an integer greater than one, comprising: a voltage controlled delay circuit for receiving the reference signal at an input terminal and generating a delay signal at an output terminal, said voltage controlled delay circuit having a control voltage input terminal, and 2N intermediate terminals for outputting signals delayed by, respectively, 1/2N, 2/2N, 3/2N, . . . 2N/2N times a delay which the delay signal has with respect to th reference signal; an N multiplying logic circuit having 2N input terminals connected to the intermediate terminals, respectively, for logically combining consecutive pairs of said intermediate signals to produce N respective output pulses for each period of said reference signal at N intermediate output terminals, wherein rising and falling edges of each of the N respective output pulses are both always triggered only by trailing edges of said intermediate signals; an adder coupled to said N intermediate output terminals and configured to combine said N respective output pulses to produce an N multiplied output signal; a synchronous circuit supplied, at a data input terminal, with the delay signal from the voltage controlled delay circuit and, at a clock input terminal, with the N multiplied output signal from the N multiplying logic circuit to produce a delay signal corresponding to the output signal; a phase comparator connected at a first input terminal to an output terminal of the synchronous circuit and supplied, at a second input terminal, with the reference signal to produce an error signal corresponding to a phase difference between both the signals; and a low pass filter supplied, at an input terminal, with the error signal from the phase comparator and having an output terminal connected to the control voltage input terminal of the voltage controlled delay circuit.

Claim 29

A frequency multiplying circuit for multiplying a frequency of a reference signal by N, N being an integer greater than one, comprising: a voltage controlled delay circuit for receiving the reference signal at an input terminal and generating a delay signal at an output terminal, said voltage controlled delay circuit having a control voltage input terminal, and 2N intermediate terminals for outputting signals delayed by, respectively, 1/2N, 2/2N, 3/2N, . . . 2N/2N times a delay which the delay signal has with respect to th reference signal; an N multiplying logic circuit having 2N input terminals connected to the intermediate terminals, respectively, for logically combining consecutive pairs of said intermediate signals to produce N respective output pulses for each period of said reference signal at N intermediate output terminals, wherein rising and falling edges of each of the N respective output pulses are both always triggered only by trailing edges of said intermediate signals; an adder coupled to said N intermediate output terminals and configured to combine said N respective output pulses to produce an N multiplied output signal; a synchronous circuit supplied, at a data input terminal, with the delay signal from the voltage controlled delay circuit and, at a clock input terminal, with the N multiplied output signal from the N multiplying logic circuit to produce a delay signal corresponding to the output signal; a phase comparator connected at a first input terminal to an output terminal of the synchronous circuit and supplied, at a second input terminal, with the reference signal to produce an error signal corresponding to a phase difference between both the signals; and a low pass filter supplied, at an input terminal, with the error signal from the phase comparator and having an output terminal connected to the control voltage input terminal of the voltage controlled delay circuit.

Claim 30

A frequency multiplying circuit according to claim 19, wherein the N multiplying logic circuit comprises an N number of flip-flop circuits connected at input terminals to the input terminals of the N multiplying logic circuit.

Claim 31

A frequency multiplying circuit for multiplying a frequency of an oscillation signal by N, N being an integer greater than one, comprising: a voltage controlled oscillator having an input terminal connected to an output terminal thereof and supplying the oscillation signal at the output terminal, said voltage controlled oscillator having N intermediate terminals for outputting respective intermediate signals delayed by, respectively, 1/2N, 2/2N, 3/2N, . . . N/2N times a period of the oscillation signal; a frequency divider connected at input terminal to the output terminal of the voltage controlled oscillator to generate a frequency divided signal from the oscillation signal; a phase comparator supplied at a first input terminal with the frequency divided signal from the frequency divider and at a second input terminal with a reference signal to generate an error signal corresponding to a phase difference between both the signals; a lowpass filter supplied at an input terminal with the error signal from the phase comparator and connected at an output terminal to a control voltage input terminal of the voltage controlled oscillator; N exclusive OR circuits each connected at a first input terminal with an output terminal of the voltage controlled oscillator and at a second input terminal to the N intermediate terminals of the voltage controlled oscillator, respectively and producing N intermediate signals at respective output terminals of said N exclusive OR circuits; an N multiplying logic circuit having N input terminals connected to the output terminals of the N exclusive OR circuits, respectively, for logically combining consecutive pairs of said intermediate signals to produce N respective output pulses for each period of said reference signal at N intermediate output terminals, wherein rising and falling edges of each of the N respective output pulses are both always triggered only by trailing edges of said intermediate signals; and an adder coupled to said intermediate output terminals ad configured to combine said N respective output pulses to produce N multiplied output signal.

Claim 32

A frequency multiplying circuit for multiplying a frequency of an oscillation signal by N, N being an integer greater than one, comprising: a voltage controlled oscillator having an input terminal connected to an output terminal thereof and supplying the oscillation signal at the output terminal, said voltage controlled oscillator having N intermediate terminals for outputting respective intermediate signals delayed by, respectively, 1/2N, 2/2N, 3/2N, . . . N/2N times a period of the oscillation signal; a frequency divider connected at input terminal to the output terminal of the voltage controlled oscillator to generate a frequency divided signal from the oscillation signal; a phase comparator supplied at a first input terminal with the frequency divided signal from the frequency divider and at a second input terminal with a reference signal to generate an error signal corresponding to a phase difference between both the signals; a lowpass filter supplied at an input terminal with the error signal from the phase comparator and connected at an output terminal to a control voltage input terminal of the voltage controlled oscillator; N exclusive OR circuits each connected at a first input terminal with an output terminal of the voltage controlled oscillator and at a second input terminal to the N intermediate terminals of the voltage controlled oscillator, respectively and producing N intermediate signals at respective output terminals of said N exclusive OR circuits; an N multiplying logic circuit having N input terminals connected to the output terminals of the N exclusive OR circuits, respectively, for logically combining consecutive pairs of said intermediate signals to produce N respective output pulses for each period of said reference signal at N intermediate output terminals, wherein rising and falling edges of each of the N respective output pulses are both always triggered only by trailing edges of said intermediate signals; and an adder coupled to said intermediate output terminals ad configured to combine said N respective output pulses to produce N multiplied output signal.

Claim 33

A frequency multiplying circuit according to claim 21, wherein the N multiplying logic circuit comprises a N/2 number of flip-flop circuits connected at input terminals to input terminals of the N multiplying logic circuit.

Claim 34

A frequency multiplying circuit for multiplying a frequency of an oscillation signal by N, N being an integer greater than one, comprising: a voltage controlled oscillator having an input terminal connected to an output terminal thereof and supplying the oscillation signal at the output terminal, said voltage controlled oscillator having N intermediate terminals for outputting signals delayed by, respectively, 1/2N, 2/2N, 3/2N, . . . N/2N times a period of the oscillation signal; a voltage controlled delay circuit connected at an input terminal to the output terminal of the voltage controlled oscillator and having N intermediate terminals for outputting signals delayed by, respectively, N+1/2N, N+2/2N, N+3/2N, . . . 2N/2N times a period of the oscillation signal; a frequency divider connected at an input terminal to the output terminal of the voltage controlled oscillator to produce a frequency divided signal from the oscillation signal; a phase comparator supplied, at a first input terminal, with the frequency divided signal from the frequency divider and, at a second input terminal, with a reference signal to produce an error signal corresponding to a phase difference between both the signals; a low pass filter supplied, at an input terminal, with the error signal and connected at an output terminal to a control voltage input terminal of the voltage controlled oscillator and to a control voltage input terminal of the voltage controlled delay circuit; an N multiplying logic circuit having 2N input terminals, N input terminals of which are connected to the N intermediate terminals of the voltage controlled oscillator and the remaining N input terminals of which are connected to the N intermediate terminals of the voltage controlled delay circuit, respectively, for logically combining consecutive pairs of said intermediate signals to produce N respective output pulses for each period of said reference signal at N intermediate terminals, wherein rising and falling edges of each of the N respective output pulses are both always triggered only by trailing edges of said intermediate signals; and an adder coupled to said N intermediate output terminals and configured to combine said N respective output pulses produce an N multiplied output signal.

Claim 35

A frequency multiplying circuit for multiplying a frequency of an oscillation signal by N, N being an integer greater than one, comprising: a voltage controlled oscillator having an input terminal connected to an output terminal thereof and supplying the oscillation signal at the output terminal, said voltage controlled oscillator having N intermediate terminals for outputting signals delayed by, respectively, 1/2N, 2/2N, 3/2N, . . . N/2N times a period of the oscillation signal; a voltage controlled delay circuit connected at an input terminal to the output terminal of the voltage controlled oscillator and having N intermediate terminals for outputting signals delayed by, respectively, N+1/2N, N+2/2N, N+3/2N, . . . 2N/2N times a period of the oscillation signal; a frequency divider connected at an input terminal to the output terminal of the voltage controlled oscillator to produce a frequency divided signal from the oscillation signal; a phase comparator supplied, at a first input terminal, with the frequency divided signal from the frequency divider and, at a second input terminal, with a reference signal to produce an error signal corresponding to a phase difference between both the signals; a low pass filter supplied, at an input terminal, with the error signal and connected at an output terminal to a control voltage input terminal of the voltage controlled oscillator and to a control voltage input terminal of the voltage controlled delay circuit; an N multiplying logic circuit having 2N input terminals, N input terminals of which are connected to the N intermediate terminals of the voltage controlled oscillator and the remaining N input terminals of which are connected to the N intermediate terminals of the voltage controlled delay circuit, respectively, for logically combining consecutive pairs of said intermediate signals to produce N respective output pulses for each period of said reference signal at N intermediate terminals, wherein rising and falling edges of each of the N respective output pulses are both always triggered only by trailing edges of said intermediate signals; and an adder coupled to said N intermediate output terminals and configured to combine said N respective output pulses produce an N multiplied output signal.

Claim 36

A frequency multiplying circuit according to claim 23, wherein the N multiplying logic circuit comprises an N number of flip-flop circuits connected at input terminals to the corresponding input terminals of the N multiplying logic circuit.