EP0477582A1
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EP
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Digital frequency multiplication and data serialization circuits
Assignee: International Business Machines Corp
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Filing: 1991-08-30
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Granted: —
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Expires: 2011-08-30
Abstract
Abstract A digital clock frequency multiplication and data serialization circuit for converting Q parallel data bits into a serial data stream is provided. A clock phase generator (34) is coupled to receive the clock signal of the Q parallel data bits and output in response thereto Q synchronous clocks each of different phase. Logic circuitry (36) is coupled to simultaneously receive the Q synchronous clocks and the Q parallel data bits. The Q synchronous clocks are used by the logic to gate a respective one of the Q parallel data bits such that the Q parallel data bits are sequentially output therefrom as a serial data stream. Circuits are provided for simultaneous frequency multiplication and return-to-zero data serialization and simultaneous frequency multiplication and nonreturn-to-zero data serialization. Further, digital clock frequency multiplication and synchronization circuits for converting a low frequency signal to a high frequency signal are described.
Inventors
- 👤 Ilya Iosephovich Novof
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-29 05:13
CPC Classifications
H; H03; H03M; H03M9/00; H03K; H03K5/00; H03K5/00006; H04; H04J; H04J3/00; H04J3/02; H04J3/04; H04J3/047; H03K2005/00013; H03K2005/0015; H03K2005/00234; H03K2005/00247; H03K2005/00286
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
145 words
A clock frequency multiplication and data serialization circuit for converting Q parallel data bits having an associated clock signal of first frequency and period into a serial data stream having a frequency which is a multiple of said first frequency, said circuit comprising: clock phase generating means (34) coupled to receive the clock signal associated with said Q parallel data bits, said generating means outputting in response thereto Q synchronous clocks each of different phase per clock signal period; and logic circuitry (36, 40) coupled to receive said Q synchronous clocks and the Q parallel data bits, said logic circuitry using each of said Q synchronous clocks to gate a respective one of said Q parallel data bits such that the Q parallel data bits are sequentially output therefrom as a serial data stream having a frequency which is a multiple of said first frequency.
Claim 2
Dependent Claim
99 words
The frequency multiplication and data serialization circuit of claim 1, wherein said logic circuitry includes: means (36) for detecting each of said Q synchronous clocks and outputting a signal pulse in response thereto; a plurality of AND gates (52), each AND gate being coupled to receive at a first input one of said signal pulses and at a second input a respective one of the parallel data bits; and OR circuit means (40) coupled to receive in parallel the output signals of said plurality of AND gates and combine said AND gate output signals into the serial data stream.
Claim 3
Dependent Claim
55 words
The frequency multiplication and data serialization circuit of claim 2, wherein said clock detecting means includes a plurality of edge detectors (62), each edge detector being coupled to receive one of said Q synchronous clocks output from said clock phase generating means, each edge detector outputting a signal pulse in response to a received clock.
Claim 4
Dependent Claim
116 words
The frequency multiplication and data serialization circuit of claim 3, wherein said clock detecting means includes Q edge detectors (36), said edge detectors each outputting a signal pulse on the rising edge of a received clock, each detector including a delay and an A not B logic circuit (62) having an A input and a B input, the A input to said A not B logic and an input to said delay each being coupled to receive one of the Q synchronous clocks, the output of said delay being coupled to the B input to said A not B logic, an output pulse from said A not B logic circuit comprising said edge detector signal pulse.
Claim 5
Dependent Claim
112 words
The frequency multiplication and data serialization circuit of claim 3, wherein said clock detecting means includes Q edge detectors, said edge detectors each outputting a signal pulse on the falling edge of a received clock, each detector including a delay and an A not B logic circuit having an A input and a B input, the B input to said A not B logic and an input to said delay being coupled to receive one of the Q synchronous clocks, the output of said delay being coupled to the A input of said A not B logic, an output pulse from said A not B logic comprising said edge detector signal pulse.
Claim 6
Dependent Claim
107 words
The frequency multiplication and data serialization circuit of claim 3, wherein said clock detecting means includes Q edge detectors, said edge detectors each outputting a signal pulse on the rising edge of a received clock, each detector including a delay, an invertor and an AND gate, one input to said AND gate and an input to said delay each being coupled to receive one of the Q synchronous clocks, the output of said delay being coupled to the input of said invertor, the invertor output being coupled to a second input to said AND gate, an output from said AND gate comprising said edge detector signal pulse.
Claim 7
Dependent Claim
111 words
The frequency multiplication and data serialization circuit of claim 3, wherein said clock detecting means includes Q edge detectors, said edge detectors each outputting a signal pulse on the falling edge of a received clock, each detector including a delay, an invertor and an AND gate, the input to said invertor and the input to said delay each being coupled to receive one of the Q synchronous clocks, the output of said invertor being coupled to a first input to said AND gate and the output of said delay being coupled to a second input to said AND gate, an output from said AND gate comprising said edge detector signal pulse.
Claim 8
Dependent Claim
37 words
The frequency multiplication and data serialization circuit of claim 2, wherein said clock phase generating means comprises a delay line having Q taps, each of said taps outputting one of said Q synchronous clocks of different phase.
Claim 9
Dependent Claim
71 words
The frequency multiplication and data serialization circuit of claim 8, wherein said detecting means comprises Q separate detecting means, an input to each of said Q detecting means being coupled to one of said delay line taps, and wherein said plurality of AND gates comprise Q AND gates, one input of each of said Q AND gates being coupled to an output of a respective one of said Q detecting means.
Claim 10
Dependent Claim
53 words
The frequency multiplication and data serialization circuit of claim 8, wherein said circuit produces return-to-zero data serialization and wherein said Q clock detecting means comprise Q edge detectors, said edge detectors each including a delay therein, each edge detector delay being less than the delay between adjacent delay clocks of the delay line.
Claim 11
Dependent Claim
92 words
The clock frequency multiplication and data serialization circuit of claim 8, wherein said circuit produces nonreturn-to-zero data serialization, and wherein said Q clock detecting means each comprises an A not B (62) logic circuit having an A input and a B input, the A input of said A not B logic being coupled to receive the f(m-1) delayed clock of the delay line and the B input to said A not B logic being coupled to receive the f(m) delayed clock of the delay line, wherein m = 1, 2, 3..., Q-1.
Claim 12
Dependent Claim
141 words
The frequency multiplication and data serialization circuit of claim 8, wherein said circuit produces a combination return to zero and nonreturn to zero data serialization, and wherein at least one of said Q clock detecting means comprises an edge detector, said edge detector including a delay therein less than a delay between adjacent delay clocks of the delay line, and wherein said Q clock detecting means includes at least one A not B logic circuit having an A input and a B input, the A input of said A not B logic being coupled to receive a first delayed clock of the delay line and the B input to said A not B logic being coupled to receive a second delayed clock of the delay line, said second delayed clock comprising the next subsequent delayed clock from said first delay clock.
References Cited (Backward Citations)
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