Patent US5953616A successfully refreshed from Google Patents.
US5953616A
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US
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Method of fabricating a MOS device with a salicide structure
Assignee: SK Hynix Inc
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Filing: 1998-05-08
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Granted: 1999-09-14
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Expires: 2018-05-08
Abstract
Abstract A method of fabricating an MOS device that includes self-aligned suicides, the method including two amorphization implantations, both of which follow formation of the self-aligned source/drain regions of the device but precede formation of the self-aligned suicides. The first consists of implantation of low-energy heavy ions, preferably of energies 15-20 keV, while the second consists of implantation of more energetic heavy ions, preferably of energies at least 40 keV.
Inventors
- 👤 Jae Gyung Ahn
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 16:49
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0212; H10B; H10B99/00; H10D30/0223; H10D30/0227; H10D30/60; H10D64/00; H10D64/01; H10D64/013; H10D64/01302; H10D64/01304; H10D64/01306; H10D64/01308; H10D64/0131
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
191 words
A method of fabricating a semiconductor device on a substrate of a first conductivity type, the substrate having a surface, the method comprising the steps of: forming a gate electrode over the surface of the substrate, the gate electrode having a surface; forming source/drain regions of a second conductivity type within the substrate to either side of the gate electrode; implanting a first species of ions of the second conductivity type with a first energy into both the gate electrode and the substrate, thereby forming first amorphous layers at the surface of the gate electrode and the surface of the substrate above the source/drain regions, respectively, wherein the first energy is selected so that the first species of ions do not pass through the gate electrode to an underlying portion of the substrate; implanting a second species of ions of the second conductivity type with a second energy into both the gate electrode and the substrate, thereby forming second amorphous layers within the substrate; and forming silicide layers at the surface of the gate electrode and at the surface of the substrate above the source/drain regions, thereby fabricating the semiconductor device.
Claim 2
Independent Claim
191 words
A method of fabricating a semiconductor device on a substrate of a first conductivity type, the substrate having a surface, the method comprising the steps of: forming a gate electrode over the surface of the substrate, the gate electrode having a surface; forming source/drain regions of a second conductivity type within the substrate to either side of the gate electrode; implanting a first species of ions of the second conductivity type with a first energy into both the gate electrode and the substrate, thereby forming first amorphous layers at the surface of the gate electrode and the surface of the substrate above the source/drain regions, respectively, wherein the first energy is selected so that the first species of ions do not pass through the gate electrode to an underlying portion of the substrate; implanting a second species of ions of the second conductivity type with a second energy into both the gate electrode and the substrate, thereby forming second amorphous layers within the substrate; and forming silicide layers at the surface of the gate electrode and at the surface of the substrate above the source/drain regions, thereby fabricating the semiconductor device.
Claim 3
Dependent Claim
16 words
The method according to claim 1, wherein the second energy is greater than the first energy.
Claim 4
Dependent Claim
22 words
The method according to claim 2, wherein the first species of ions is the same as the second species of heavy ions.
Claim 5
Dependent Claim
17 words
The method according to claim 3, wherein the first energy is no greater than aproximately 20 keV.
Claim 6
Dependent Claim
14 words
The method according to claim 4, wherein the first energy is aproximately 15-20 keV.
Claim 7
Dependent Claim
17 words
The method according to claim 5, wherein the first amorphous layers have thicknesses of aproximately 50-300 Å.
Claim 8
Dependent Claim
16 words
The method according to claim 2, wherein the second energy is at least aproximately 40 keV.
Claim 9
Independent Claim
16 words
The method according to claims 3, wherein the second energy is at least aproximately 40 keV.
Claim 10
Dependent Claim
16 words
The method according to claim 4, wherein the second energy is at least aproximately 40 keV.
Claim 11
Dependent Claim
16 words
The method according to claim 5, wherein the second energy is at least aproximately 40 keV.
Claim 12
Dependent Claim
16 words
The method according to claim 6, wherein the second energy is at least aproximately 40 keV.
Claim 13
Dependent Claim
42 words
The method according to claim 1, wherein the first energy is selected so that the first amorphous layers are formed as continuous amorphous layers at the surface of the gate electrode and the surface of the substrate above the source/drain regions, respectively.
Claim 14
Dependent Claim
59 words
The method according to claim 1, wherein the first energy is selected so that the first amorphous layers are continuous and have a thickness that allow scattereing of the second species of ions implanted into the gate electrode so that the second species of ions do not pass through the gate electrode to an underlying portion of the substrate.
Claim 15
Dependent Claim
36 words
The method according to claim 1, wherein the second energy is selected so that the second species of ions penetrate a greater distance into the gate electrode and the substrate than the first species of ions.
Claim 16
Dependent Claim
33 words
The method according to claim 14, wherein the second energy is selected so that the second species of ions do not pass through the gate electrode to an underlying portion of the substrate.
Claim 17
Independent Claim
125 words
A method of fabricating a semiconductor device, comprising the steps of: forming a gate electrode on a surface of a substrate; forming source/drain regions in the substrate on either side of the gate electrode; implanting a first species of ions having a first energy into the gate electrode and the substrate to form continuous amorphous layers on a top surface of the gate electrode and the surface of the substrate; and implanting a second species of ions having a second energy, greater than the first energy, into the gate electrode and the substrate so that the second species of ions penetrate further into the top surface of the gate electrode and the substrate to form deeper amorphous layers in the gate electrode and the substrate.
Claim 18
Independent Claim
125 words
A method of fabricating a semiconductor device, comprising the steps of: forming a gate electrode on a surface of a substrate; forming source/drain regions in the substrate on either side of the gate electrode; implanting a first species of ions having a first energy into the gate electrode and the substrate to form continuous amorphous layers on a top surface of the gate electrode and the surface of the substrate; and implanting a second species of ions having a second energy, greater than the first energy, into the gate electrode and the substrate so that the second species of ions penetrate further into the top surface of the gate electrode and the substrate to form deeper amorphous layers in the gate electrode and the substrate.
Claim 19
Dependent Claim
52 words
The method of claim 16, wherein the step of implanting a first species of ions is conducted with a first energy for formation of an amorphous layer on the gate electrode that will prevent the second species of ions from passing through the gate electrode to an underlying portion of the substrate.
Claim 20
Dependent Claim
15 words
The method of claim 16, wherein the first energy is less than approximately 20 keV.
Claim 21
Dependent Claim
15 words
The method of claim 18, wherein the second energy is more than approximately 40 keV.
Claim 22
Dependent Claim
32 words
The method of claim 16, wherein the second energy is selected to that the second species of ions do not pass through the gate electrode to an underlying portion of the substrate.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-09-13 | 2003-03-15 | 2003-09-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-09-13 | 2007-03-15 | 2007-09-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-09-13 | 2011-03-15 | 2011-09-14 | $7700.00 | Window Closed / Lapsed |