US5949797A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Microcontroller test circuit
Assignee: Samsung Electronics Co Ltd
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Filing: 1995-12-15
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Granted: 1999-09-07
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Expires: 2015-12-15
Abstract
Abstract A microcontroller test circuit having a plurality of pins includes first circuit for determining whether the microcontroller is in a normal mode or a test mode by sensing the potential of an input test signal; and second circuit for selectively opening a first path for making a first pin of the plurality of pins a signal output pin when the input signal is at a first potential and for opening a second path for making the first pin a test signal input pin when the input signal is at a second potential. In this way, the test circuit uses an existing pin that would not otherwise be used during testing instead of requiring a separate test pin.
Inventors
- 👤 Kwang-Jae Jung
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 15:12
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/31701; G01R31/31712; G01R31/31713
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
97 words
A test circuit for a microcontroller having a plurality of pins, the test circuit comprising: first means for determining whether the microcontroller is in a normal mode or a test mode by sensing the potential of an input test signal; and second means for selectively opening a first path for making a first pin of the plurality of pins a signal output pin when the input signal is at a first potential and for opening a second path for making the first pin a test signal input pin when the input signal is at a second potential.
Claim 2
Dependent Claim
97 words
A test circuit for a microcontroller having a plurality of pins, the test circuit comprising: first means for determining whether the microcontroller is in a normal mode or a test mode by sensing the potential of an input test signal; and second means for selectively opening a first path for making a first pin of the plurality of pins a signal output pin when the input signal is at a first potential and for opening a second path for making the first pin a test signal input pin when the input signal is at a second potential.
Claim 3
Dependent Claim
22 words
The test circuit of claim 1, wherein the first means comprises a plurality of voltage drop components serially connected to one another.
Claim 4
Dependent Claim
29 words
The test circuit of claim 1, further comprising gate means connected to the second path, for generating a plurality of test signals in response to the input test signal.
Claim 5
Dependent Claim
55 words
The test circuit of claim 3, wherein the second means comprises a first transmission gate placed on the first path and connected between the first pin and a second pin of the plurality of pins, and a second transmission gate placed on the second path and connected between the first pin and the gate means.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-09-06 | 2003-03-08 | 2003-09-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-09-06 | 2007-03-08 | 2007-09-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-09-06 | 2011-03-08 | 2011-09-07 | $7700.00 | Window Closed / Lapsed |