US5420869A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor integrated circuit device
Assignee: Fujitsu Ltd
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Filing: 1994-05-11
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Granted: 1995-05-30
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Expires: 2014-05-11
Abstract
Abstract A semiconductor integrated circuit device includes an external connection terminal receiving a normal signal varying between a high potential and a low potential, and a test mode setting signal, an input circuit which is connected to the external connection terminal and receives the normal signal via the external connection terminal, an n-channel field effect transistor having a gate connected to the external connection terminal, a drain coupled to a first voltage line via a load element, and a source connected to a second voltage line. The second voltage line is at a potential approximately equal to said high potential. The first voltage line is at a potential equal to or higher than the sum of the high potential and a threshold voltage of the n-channel field effect transistor. The test mode setting signal of a potential equal to or higher than the sum of the high potential and the threshold voltage is applied to the n-channel field effect transistor. A test mode setting signal detecting signal used to initiate a test of the semiconductor integrated circuit device is output via the drain of the n-channel field effect transistor.
Inventors
- 👤 Atsushi Hatakeyama
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 15:53
CPC Classifications
G; G01; G01R; G01R19/00; G01R19/165; G01R19/16504; G01R19/16519; G01R31/00; G01R31/28; G01R31/317; G01R31/31701
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
188 words
A semiconductor integrated circuit device comprising: an external connection terminal receiving a normal signal varying between a high potential and a low potential, and a test mode setting signal; an input circuit which is connected to the external connection terminal and receives the normal signal via the external connection terminal; an n-channel field effect transistor having a gate connected to the external connection terminal, a drain coupled to a first voltage line via a load element, and a source connected to a second voltage line, the second voltage line being at a potential approximately equal to said high potential, the first voltage line being at a potential equal to or higher than a sum of the high potential and a threshold voltage of the n-channel field effect transistor, the test mode setting signal of a potential equal to or higher than the sum of the high potential and the threshold voltage being applied to the n-channel field effect transistor, a test mode setting signal detecting signal used to initiate a test of the semiconductor integrated circuit device being output via the drain of the n-channel field effect transistor.
Claim 2
Dependent Claim
188 words
A semiconductor integrated circuit device comprising: an external connection terminal receiving a normal signal varying between a high potential and a low potential, and a test mode setting signal; an input circuit which is connected to the external connection terminal and receives the normal signal via the external connection terminal; an n-channel field effect transistor having a gate connected to the external connection terminal, a drain coupled to a first voltage line via a load element, and a source connected to a second voltage line, the second voltage line being at a potential approximately equal to said high potential, the first voltage line being at a potential equal to or higher than a sum of the high potential and a threshold voltage of the n-channel field effect transistor, the test mode setting signal of a potential equal to or higher than the sum of the high potential and the threshold voltage being applied to the n-channel field effect transistor, a test mode setting signal detecting signal used to initiate a test of the semiconductor integrated circuit device being output via the drain of the n-channel field effect transistor.
Claim 3
Dependent Claim
53 words
The semiconductor integrated circuit device as claimed in claim 1, further comprising level conversion means for converting a level of the test mode setting signal detecting signal into an activating signal which has a logical level of an internal circuit of the semiconductor integrated circuit device and is applied to the internal circuit.
Claim 4
Dependent Claim
22 words
The semiconductor integrated circuit device as claimed in claim 2, wherein said level conversion means comprises a plurality of level conversion stages.
Claim 5
Dependent Claim
41 words
The semiconductor integrated circuit device as claimed in claim 1, further comprising level conversion means for converting a level of the test mode setting signal detecting signal into an activating signal which varies between the high potential and the low potential.
Claim 6
Dependent Claim
18 words
The semiconductor integrated circuit device as claimed in claim 1, wherein the load element comprises a CMOS inverter.
Claim 7
Dependent Claim
84 words
The semiconductor integrated circuit device as claimed in claim 1, further comprising: a memory cell array; access means for accessing the memory cell array for writing data into the memory cell array and reading data therefrom; input/output means for supplying write data to the memory cell array and for outputting read data to the outside of the semiconductor integrated circuit device; and test means for performing a test of the semiconductor integrated circuit device in response to the test mode setting signal detecting signal.
Claim 8
Dependent Claim
188 words
A semiconductor integrated circuit device comprising: an external connection terminal receiving a normal signal varying between a high potential and a low potential, and a test mode setting signal; an input circuit which is connected to the external connection terminal and receives the normal signal via the external connection terminal; a p-channel field effect transistor having a gate connected to the external connection terminal, a source coupled to a first voltage line, and a drain connected to a second voltage line via a current source, the first voltage line being at a potential approximately equal to said low potential, the second voltage line being at a potential equal to or lower than a sum of the low potential and a threshold voltage of the p-channel field effect transistor, the test mode setting signal of a potential equal to or lower than the sum of the low potential and the threshold voltage being applied to the p-channel field effect transistor, a test mode setting signal detecting signal used to initiate a test of the semiconductor integrated circuit device being output via the drain of the p-channel field effect transistor.
Claim 9
Dependent Claim
188 words
A semiconductor integrated circuit device comprising: an external connection terminal receiving a normal signal varying between a high potential and a low potential, and a test mode setting signal; an input circuit which is connected to the external connection terminal and receives the normal signal via the external connection terminal; a p-channel field effect transistor having a gate connected to the external connection terminal, a source coupled to a first voltage line, and a drain connected to a second voltage line via a current source, the first voltage line being at a potential approximately equal to said low potential, the second voltage line being at a potential equal to or lower than a sum of the low potential and a threshold voltage of the p-channel field effect transistor, the test mode setting signal of a potential equal to or lower than the sum of the low potential and the threshold voltage being applied to the p-channel field effect transistor, a test mode setting signal detecting signal used to initiate a test of the semiconductor integrated circuit device being output via the drain of the p-channel field effect transistor.
Claim 10
Dependent Claim
53 words
The semiconductor integrated circuit device as claimed in claim 7, further comprising level conversion means for converting a level of the test mode setting signal detecting signal into an activating signal which has a logical level of an internal circuit of the semiconductor integrated circuit device and is applied to the internal circuit.
Claim 11
Dependent Claim
22 words
The semiconductor integrated circuit device as claimed in claim 8, wherein said level conversion means comprises a plurality of level conversion stages.
Claim 12
Dependent Claim
41 words
The semiconductor integrated circuit device as claimed in claim 7, further comprising level conversion means for converting a level of the test mode setting signal detecting signal into an activating signal which varies between the high potential and the low potential.
Claim 13
Dependent Claim
27 words
The semiconductor integrated circuit device as claimed in claim 7, wherein the current source comprises a field effect transistor having a gate set to the high potential.
Claim 14
Dependent Claim
84 words
The semiconductor integrated circuit device as claimed in claim 7, further comprising: a memory cell array; access means for accessing the memory cell array for writing data into the memory cell array and reading data therefrom; input/output means for supplying write data to the memory cell array and for outputting read data to the outside of the semiconductor integrated circuit device; and test means for performing a test of the semiconductor integrated circuit device in response to the test mode setting signal detecting signal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-05-29 | 1998-11-28 | 1999-05-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-05-29 | 2002-11-28 | 2003-05-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-05-29 | 2006-11-28 | 2007-05-30 | $7700.00 | Window Closed / Lapsed |