Level detector circuit for microcomputer devices

Claim 2

A level detector circuit for a microcomputer input terminal or the like, comprising: a bistable latch having first and second unbalanced input nodes and an output; said input nodes being unbalanced by impedance means of unequal value connected to the nodes; means for precharging said first and second input nodes to equal voltage; a first transistor having a current path connecting said first input node to ground and having a gate connected to said input terminal; a second transistor having a current path connecting said second input node to ground and having a gate connected to a first logic level; and means for gating said current paths of the first and second transistors to a conductive condition after said means for precharging has precharged said input nodes, whereby said bistable latch flips to one stable state if the input terminal is at a voltage substantially above said first logic level, or flips to another stable state if the input terminal is at about said first logic level or below.

Claim 3

A circuit according to claim 1 wherein said first and second transistors are insulated gate field effect transistors and the current paths are source-to-drain paths.

Claim 4

A circuit according to claim 1 wherein said means for precharging comprises a pair of transistors, said pair of transistors having source-to-drain paths connected in series with said current paths of said first and second transistors and a voltage supply, and said pair of transistors having gates connected to a first clock.

Claim 5

A circuit according to claim 3 wherein said means for gating comprises a second pair of transistors, said second pair of transistors having source-to-drain paths in series with said current paths of the first and second transistors, and said second pair of transistors having gates connected to a second clock, said second clock occurring after said first clock.

Claim 6

A circuit according to claim 4 wherein said impedance means are capacitors of unequal value.

Claim 7

A level detector circuit for a microcomputer input terminal or the like, comprising: (a) a first bistable latch having first and second unbalanced input nodes and an output; said input nodes being unbalanced by impedance means of unequal value connected to the nodes; means for precharging said first and second input nodes to equal voltage; a first transistor having a current path connecting said first input node to ground and having a gate connected to said input terminal; a second transistor having a current path connecting said second input node to ground and a gate connected to a first logic level; and means for gating said current paths of the first and second transistors to a conductive condition after said means for precharging has precharged said input nodes, whereby said latch flips to one stable state if the input terminal is at a voltage substantially above said first logic level, or flips to another stable state if the input terminal is at about said first logic level or below, and (b) a second bistable latch having an input connected to said input terminal through a threshold-responsive trigger set at a level above ground and below said first logic level, and having an output, whereby said output of the first bistable latch and said output of the second bistable latch together define a three-level detection output.

Claim 8

A level detector circuit for a microcomputer input terminal or the like, comprising: (a) a first bistable latch having first and second unbalanced input nodes and an output; said input nodes being unbalanced by impedance means of unequal value connected to the nodes; means for precharging said first and second input nodes to equal voltage; a first transistor having a current path connecting said first input node to ground and having a gate connected to said input terminal; a second transistor having a current path connecting said second input node to ground and a gate connected to a first logic level; and means for gating said current paths of the first and second transistors to a conductive condition after said means for precharging has precharged said input nodes, whereby said latch flips to one stable state if the input terminal is at a voltage substantially above said first logic level, or flips to another stable state if the input terminal is at about said first logic level or below, and (b) a second bistable latch having an input connected to said input terminal through a threshold-responsive trigger set at a level above ground and below said first logic level, and having an output, whereby said output of the first bistable latch and said output of the second bistable latch together define a three-level detection output.

Claim 9

A circuit according to claim 1 wherein said first logic level is a supply voltage, and said means for precharging precharges said first and second input nodes from said supply voltage.