Semiconductor memory device comprising multi-level logic value of the threshold voltage

Claim 2

A semiconductor memory device comprising: a semiconductor substrate; an array of a plurality of memory cells formed and arranged on said semiconductor substrate, each memory cell including a first transistor; element separating trenches arranged in at least part of each of said plurality of memory cells, each of said element separating trenches having an element separating insulative film and an electrically conductive film formed on said element separating insulative film; a second transistor arranged at a part of a first lateral side of each of said plurality of memory cells, and including said electrically conductive film as a control gate and diffusion layers of a source and a drain; and a third transistor arranged at a part of a second lateral side of each of said plurality of memory cells and including said electrically conductive film as a control gate and diffusion layers of a source and a drain, wherein said diffusion layers of sources and drains of said second and said third transistors are connected in parallel, and a threshold voltage of said second transistor is set to a first voltage which is higher than a second voltage applied to the control gate of the second transistor corresponding to a selected memory cell in a read operation.

Claim 3

A semiconductor memory device according to claim 1, wherein source and drain diffusion layers of said first transistor of said memory cell are shared and a plurality of said first transistors of said memory cells are connected in parallel.

Claim 4

A semiconductor memory device according to claim 2, wherein said plurality of memory cells connected in parallel are coupled to a data line via a common select transistor.

Claim 5

A semiconductor memory device according to claim 1, wherein source and drain diffusion layers of said first transistor of said memory cells are shared and a plurality of said first transistors of said memory cells are connected in series.

Claim 6

A semiconductor memory device according to claim 4, wherein said plurality of memory cells connected in parallel are coupled to a data line via a common select transistor.

Claim 7

A semiconductor memory device comprising: a semiconductor substrate; an array of a plurality of memory cells formed and arranged on said semiconductor substrate, each memory cell including a first transistor; element separating trenches arranged in at least part of each of said plurality of memory cells, each of said element separating trenches having an element separating insulative film and an electrically conductive film formed on said element separating insulative film; a second transistor arranged at a part of a first lateral side of each of said plurality of memory cells, and including said electrically conductive film as a control gate and diffusion layers of a source and a drain; and a third transistor arranged at a part of a second lateral side of each of said plurality of memory cells and including said electrically conductive film as a control gate and diffusion layers of a source and a drain, wherein said diffusion layers of sources and drains of said second and third transistors are shared, said diffusion layers of sources and drains of said second and said third transistors are connected in series, said second transistor, said third transistor, and said first transistor are connected in series, and a threshold voltage of said second transistor is set to a first voltage which is lower than a second voltage applied to the control gate of the second transistor corresponding to a selected memory cell in a read operation.

Claim 8

A semiconductor memory device comprising: a semiconductor substrate; an array of a plurality of memory cells formed and arranged on said semiconductor substrate, each memory cell including a first transistor; element separating trenches arranged in at least part of each of said plurality of memory cells, each of said element separating trenches having an element separating insulative film and an electrically conductive film formed on said element separating insulative film; a second transistor arranged at a part of a first lateral side of each of said plurality of memory cells, and including said electrically conductive film as a control gate and diffusion layers of a source and a drain; and a third transistor arranged at a part of a second lateral side of each of said plurality of memory cells and including said electrically conductive film as a control gate and diffusion layers of a source and a drain, wherein said diffusion layers of sources and drains of said second and third transistors are shared, said diffusion layers of sources and drains of said second and said third transistors are connected in series, said second transistor, said third transistor, and said first transistor are connected in series, and a threshold voltage of said second transistor is set to a first voltage which is lower than a second voltage applied to the control gate of the second transistor corresponding to a selected memory cell in a read operation.

Claim 9

A semiconductor memory device according to claim 6, wherein source and drain diffusion layers of said first transistor of said memory cell are shared and a plurality of said first transistors of said memory cells are connected in parallel.

Claim 10

A semiconductor memory device according to claim 7, wherein said plurality of memory cells connected in parallel are coupled to a data line via a common select transistor.

Claim 11

A semiconductor memory device according to claim 6, wherein source and drain diffusion layers of said first transistor of said memory cells are shared and a plurality of said first transistors of said memory cells are connected in series.

Claim 12

A semiconductor memory device according to claim 9, wherein said plurality of memory cells connected in parallel are coupled to a data line via a common select transistor.

Claim 13

A non-volatile semiconductor memory device comprising: a semiconductor substrate; and an array of a plurality of memory cells formed and arranged on said semiconductor substrate, each memory cell including a first transistor having a control gate, each of said memory cells including a charge storage layer formed on said semiconductor substrate with a first insulative layer arranged therebetween and a first electrically conductive layer formed on said charge storage layer with a second insulative layer arranged therebetween; wherein said semiconductor substrate includes element separating regions arranged between any two adjacent ones of said plurality of memory cells, each of said regions including an element separating trench therein in which is embedded in at least a portion of the trench an element separating insulative film, and in which is embedded a second electrically conductive layer in at least part of the remaining portion of the trench, said charge storage layer is arranged above a first channel region of a surface of said semiconductor substrate and said first transistor is constructed by said first electrically conductive layer formed as said control gate, said second electrically conductive layer is arranged above a second channel region at said part of the remaining portion of the trench, and a second transistor is constructed by said second electrically conductive layer formed as a second gate, source and drain diffusion layers of said first transistor having said first channel region and said second transistor having said second channel region are shared and said first and second transistors are connected in parallel to construct said memory cell, each of a plurality of said memory cells stores an n-level logic value (where n is a natural number) having 2 or more levels, and a threshold voltage of said second transistor, which has said second channel region, having said second electrically conductive layer formed as a second gate is set to a first voltage which is higher than a second voltage applied to the second gate of the second transistor corresponding to a selected memory cell in a read operation for deciding a highest level of threshold value and a second highest level thereof.

Claim 14

A non-volatile semiconductor memory device comprising: a semiconductor substrate; and an array of a plurality of memory cells formed and arranged on said semiconductor substrate, each memory cell including a first transistor having a control gate, each of said memory cells including a charge storage layer formed on said semiconductor substrate with a first insulative layer arranged therebetween and a first electrically conductive layer formed on said charge storage layer with a second insulative layer arranged therebetween; wherein said semiconductor substrate includes element separating regions arranged between any two adjacent ones of said plurality of memory cells, each of said regions including an element separating trench therein in which is embedded in at least a portion of the trench an element separating insulative film, and in which is embedded a second electrically conductive layer in at least part of the remaining portion of the trench, said charge storage layer is arranged above a first channel region of a surface of said semiconductor substrate and said first transistor is constructed by said first electrically conductive layer formed as said control gate, said second electrically conductive layer is arranged above a second channel region at said part of the remaining portion of the trench, and a second transistor is constructed by said second electrically conductive layer formed as a second gate, source and drain diffusion layers of said first transistor having said first channel region and said second transistor having said second channel region are shared and said first and second transistors are connected in parallel to construct said memory cell, each of a plurality of said memory cells stores an n-level logic value (where n is a natural number) having 2 or more levels, and a threshold voltage of said second transistor, which has said second channel region, having said second electrically conductive layer formed as a second gate is set to a first voltage which is higher than a second voltage applied to the second gate of the second transistor corresponding to a selected memory cell in a read operation for deciding a highest level of threshold value and a second highest level thereof.

Claim 15

A semiconductor memory device according to claim 11, wherein source and drain diffusion layers of said first transistor of said memory cell are shared and a plurality of said first transistors of said memory cells are connected in parallel.

Claim 16

A semiconductor memory device according to claim 12, wherein said plurality of memory cells connected in parallel are coupled to a data line via a common select transistor.

Claim 17

A semiconductor memory device according to claim 11, wherein number of said levels is 2.

Claim 18

A semiconductor memory device according to claim 11, wherein said storage layer is formed by a polysilicon film.

Claim 19

A semiconductor memory device according to claim 11, wherein said first and second insulative layers are formed by one of a silicon nitride film and SiO 2 film.

Claim 20

A non-volatile semiconductor memory device comprising: a semiconductor substrate; and an array of a plurality of memory cells formed and arranged on said semiconductor substrate, each memory cell including a first transistor having a control gate, each of said memory cells including a charge storage layer formed on said semiconductor substrate with a first insulative layer arranged therebetween and a first electrically conductive layer formed on said charge storage layer with a second insulative layer arranged therebetween; wherein said semiconductor substrate includes element separating regions arranged between any two adjacent ones of said plurality of memory cells, each of said regions including an element separating trench therein in which is embedded in at least a portion of the trench an element separating insulative film, and in which is embedded a second electrically conductive layer in at least part of the remaining portion of the trench, said charge storage layer is arranged above a first channel region of a surface of said semiconductor substrate and said first transistor is constructed by said first electrically conductive layer formed as said control gate, said second electrically conductive layer is arranged above a second channel region at said part of the remaining portion of the trench, and a second transistor is constructed by said second electrically conductive layer formed as a second gate, source and drain diffusion layers of said first transistor having said first channel region and said second transistor having said second channel region are shared and said first and second transistors are connected in parallel to construct said memory cell, source and drain diffusion layers of adjacent memory cells of said memory cells are shared and a plurality of memory cells are connected in series to construct NAND cell, each of a plurality of said memory cells stores an n-level logic value (where n is a natural number) having 2 or more levels, and a threshold voltage of said second transistor, which has said second channel region, having said second electrically conductive layer formed as a second gate is set to a first voltage which is higher than a second voltage applied to the second gate of the second transistor corresponding, to a selected memory cell in a read operation for deciding a highest level of threshold value and a second highest level thereof and is set to a third voltage which is lower than a fourth voltage applied to a control gate of an unselected memory cell of a selected NAND cell in a read operation.

Claim 21

A non-volatile semiconductor memory device comprising: a semiconductor substrate; and an array of a plurality of memory cells formed and arranged on said semiconductor substrate, each memory cell including a first transistor having a control gate, each of said memory cells including a charge storage layer formed on said semiconductor substrate with a first insulative layer arranged therebetween and a first electrically conductive layer formed on said charge storage layer with a second insulative layer arranged therebetween; wherein said semiconductor substrate includes element separating regions arranged between any two adjacent ones of said plurality of memory cells, each of said regions including an element separating trench therein in which is embedded in at least a portion of the trench an element separating insulative film, and in which is embedded a second electrically conductive layer in at least part of the remaining portion of the trench, said charge storage layer is arranged above a first channel region of a surface of said semiconductor substrate and said first transistor is constructed by said first electrically conductive layer formed as said control gate, said second electrically conductive layer is arranged above a second channel region at said part of the remaining portion of the trench, and a second transistor is constructed by said second electrically conductive layer formed as a second gate, source and drain diffusion layers of said first transistor having said first channel region and said second transistor having said second channel region are shared and said first and second transistors are connected in parallel to construct said memory cell, source and drain diffusion layers of adjacent memory cells of said memory cells are shared and a plurality of memory cells are connected in series to construct NAND cell, each of a plurality of said memory cells stores an n-level logic value (where n is a natural number) having 2 or more levels, and a threshold voltage of said second transistor, which has said second channel region, having said second electrically conductive layer formed as a second gate is set to a first voltage which is higher than a second voltage applied to the second gate of the second transistor corresponding, to a selected memory cell in a read operation for deciding a highest level of threshold value and a second highest level thereof and is set to a third voltage which is lower than a fourth voltage applied to a control gate of an unselected memory cell of a selected NAND cell in a read operation.

Claim 22

A semiconductor memory device according to claim 17, wherein said plurality of memory cells connected in series are coupled to a data line via a common select transistor.

Claim 23

A semiconductor memory device according to claim 17, wherein number of said levels is 2.

Claim 24

A semiconductor memory device according to claim 17, wherein said storage layer is formed by a polysilicon film.

Claim 25

A semiconductor memory device according to claim 17, wherein said first and second insulative layers are formed by one of a silicon nitride film and SiO 2 film.

Claim 26

A non-volatile semiconductor memory device comprising: a semiconductor substrate, and an array of a plurality of memory cells formed and arranged on said semiconductor substrate, each memory cell including a first transistor having a control gate, each of said memory cells including a charge storage layer formed on said semiconductor substrate with a first insulative layer arranged therebetween and a first electrically conductive layer formed on said charge storage layer with a second insulative layer arranged therebetween; wherein said semiconductor substrate includes element separating regions arranged between any two adjacent ones of said plurality of memory cells, each of said regions including an element separating trench therein in which is embedded in at least a portion of the trench an element separating insulative film, and in which is embedded a second electrically conductive layer in at least part of the remaining portion of the trench, said charge storage layer is arranged above a first channel region of a surface of said semiconductor substrate and said first transistor is constructed by said first electrically conductive layer formed as said control gate, said second electrically conductive layer is arranged above a second channel region at said part of the remaining portion of the trench, and a second transistor is constructed by said second electrically conductive layer formed as a second gate, source and drain diffusion layers of said first transistor having said first channel region and said second transistor having said second channel region are shared and said first and second transistors are connected in series to construct said memory cell, each of a plurality of said memory cells stores an n-level logic value (where n is a natural number) having 2 or more levels, and a threshold voltage of said second transistor, which has said second channel region, having said second electrically conductive layer formed as a second gate is set to a first voltage which is lower than a second voltage applied to the second gate of the second transistor corresponding to a selected memory cell in a read operation for deciding a lowest level of threshold value and a second lowest level thereof.

Claim 27

A non-volatile semiconductor memory device comprising: a semiconductor substrate, and an array of a plurality of memory cells formed and arranged on said semiconductor substrate, each memory cell including a first transistor having a control gate, each of said memory cells including a charge storage layer formed on said semiconductor substrate with a first insulative layer arranged therebetween and a first electrically conductive layer formed on said charge storage layer with a second insulative layer arranged therebetween; wherein said semiconductor substrate includes element separating regions arranged between any two adjacent ones of said plurality of memory cells, each of said regions including an element separating trench therein in which is embedded in at least a portion of the trench an element separating insulative film, and in which is embedded a second electrically conductive layer in at least part of the remaining portion of the trench, said charge storage layer is arranged above a first channel region of a surface of said semiconductor substrate and said first transistor is constructed by said first electrically conductive layer formed as said control gate, said second electrically conductive layer is arranged above a second channel region at said part of the remaining portion of the trench, and a second transistor is constructed by said second electrically conductive layer formed as a second gate, source and drain diffusion layers of said first transistor having said first channel region and said second transistor having said second channel region are shared and said first and second transistors are connected in series to construct said memory cell, each of a plurality of said memory cells stores an n-level logic value (where n is a natural number) having 2 or more levels, and a threshold voltage of said second transistor, which has said second channel region, having said second electrically conductive layer formed as a second gate is set to a first voltage which is lower than a second voltage applied to the second gate of the second transistor corresponding to a selected memory cell in a read operation for deciding a lowest level of threshold value and a second lowest level thereof.

Claim 28

A semiconductor memory device according to claim 22, wherein source and drain diffusion layers of said first transistor of said memory cell are shared and a plurality of said first transistors of said memory cells are connected in series.

Claim 29

A semiconductor memory device according to claim 23, wherein said plurality of memory cells connected in parallel are coupled to a data line via a common select transistor.

Claim 30

A semiconductor memory device according to claim 22, wherein number of said levels is 2.

Claim 31

A semiconductor memory device according to claim 22, wherein said storage layer is formed by a polysilicon film.

Claim 32

A semiconductor memory device according to claim 22, wherein said first and second insulative layers are formed by one of a silicon nitride film and multilayered film of silicon nitride film and SiO 2 film.

Claim 33

A non-volatile semiconductor memory device comprising: a semiconductor substrate; and an array of a plurality of memory cells formed and arranged on said semiconductor substrate, each memory cell including a first transistor having a control gate, each of said memory cells including a charge storage layer formed on said semiconductor substrate with a first insulative layer arranged therebetween and a first electrically conductive layer formed on said charge storage layer with a second insulative layer arranged therebetween; wherein said semiconductor substrate includes element separating regions arranged between any two adjacent ones of said plurality of memory cells, regions including an element separating trench in which is embedded in at least a portion of the trench an element separating insulative film, and in which is embedded a second electrically conductive layer in at least part of the remaining portion of the trench, said charge storage layer is arranged above a first channel region of a surface of said semiconductor substrate in a direction of a channel width and a first transistor is constructed by said first electrically conductive layer formed as a control gate, said second electrically conductive layer is arranged above a second channel region at said part of the remaining portion of the trench, and a second transistor is constructed by said second electrically conductive layer formed as a second gate, source and drain diffusion layers of said first transistor having said first channel region and said second transistor having said second channel region are shared and said first and second transistors are connected in series to construct said memory cell, source and drain diffusion layers of adjacent memory cells of said memory cells are shared and a plurality of memory cells are connected in parallel, each of a plurality of said memory cells stores an n-level logic value (wherein n is a natural number) having 2 or more levels, and a threshold voltage of said second transistor, which has said second channel region, having said second electrically conductive layer formed as a second gate is set to a first voltage which is lower than a second voltage applied to the second gate of the second transistor corresponding to a selected memory cell in a read operation for deciding a lowest level of threshold value and a second lowest level thereof and is set to a third voltage which is higher than a fourth voltage applied to a control gate of an unselected memory cell.

Claim 34

A non-volatile semiconductor memory device comprising: a semiconductor substrate; and an array of a plurality of memory cells formed and arranged on said semiconductor substrate, each memory cell including a first transistor having a control gate, each of said memory cells including a charge storage layer formed on said semiconductor substrate with a first insulative layer arranged therebetween and a first electrically conductive layer formed on said charge storage layer with a second insulative layer arranged therebetween; wherein said semiconductor substrate includes element separating regions arranged between any two adjacent ones of said plurality of memory cells, regions including an element separating trench in which is embedded in at least a portion of the trench an element separating insulative film, and in which is embedded a second electrically conductive layer in at least part of the remaining portion of the trench, said charge storage layer is arranged above a first channel region of a surface of said semiconductor substrate in a direction of a channel width and a first transistor is constructed by said first electrically conductive layer formed as a control gate, said second electrically conductive layer is arranged above a second channel region at said part of the remaining portion of the trench, and a second transistor is constructed by said second electrically conductive layer formed as a second gate, source and drain diffusion layers of said first transistor having said first channel region and said second transistor having said second channel region are shared and said first and second transistors are connected in series to construct said memory cell, source and drain diffusion layers of adjacent memory cells of said memory cells are shared and a plurality of memory cells are connected in parallel, each of a plurality of said memory cells stores an n-level logic value (wherein n is a natural number) having 2 or more levels, and a threshold voltage of said second transistor, which has said second channel region, having said second electrically conductive layer formed as a second gate is set to a first voltage which is lower than a second voltage applied to the second gate of the second transistor corresponding to a selected memory cell in a read operation for deciding a lowest level of threshold value and a second lowest level thereof and is set to a third voltage which is higher than a fourth voltage applied to a control gate of an unselected memory cell.

Claim 35

A semiconductor memory device according to claim 28, wherein said plurality of memory cells connected in parallel are coupled to a data line via a common select transistor.

Claim 36

A semiconductor memory device according to claim 28, wherein number of said levels is 2.

Claim 37

A semiconductor memory device according to claim 28, wherein said storage layer is formed by a polysilicon film.

Claim 38

A semiconductor memory device according to claim 28, wherein said first and second insulative layers are formed by one of a silicon nitride film and multilayered film of silicon nitride film and SiO 2 film.