Semiconductor device having inversion inducing gate

Claim 2

A semiconductor device comprising: a semiconductor substrate; a first insulating film formed on said semiconductor substrate; a plurality of first conductive layers formed on said semiconductor substrate through said first insulating film, each of said first conductive layers functioning as a gate; a second insulating film formed on upper and side surfaces of each of said plurality of first conductive layers; a second conductive film formed in common on at least the side surface of a selected number of said plurality of first conductive layers through said second insulating film to form a plurality of inversion layers on a surface region of said substrate, wherein when a predetermined voltage is applied to said second conductive film, said inversion layers are formed on the surface region of said substrate and provide a source and drain and a plurality of transistors are formed by said first conductive layer functioning as a gate and said inversion layers functioning as the source and the drain; and voltage supply means connected to said second conductive film for applying said predetermined voltage to said second conductive layer.

Claim 3

A device according to claim 1 2, wherein at least one said transistor providing at least one further including a charge storage layer formed between said first insulating film and said first conductive layer so that an electrical rewrite operation can be performed by changing charges of said charge or storage layer, and said second conductive film is formed on a side surface of said charge storage layer.

Claim 4

A device according to claim 2, wherein a plurality of said transistors are connected in series with each other to constitute a NAND cell.

Claim 5

A device according to claim 2, wherein a plurality of said transistors are connected in parallel with each other to constitute one unit memory cell.

Claim 6

A device according to claim 2, wherein, a plurality of said transistors are divided into a plurality of blocks and said conductive films are formed for each block, and further comprises; means, in one of a data read mode, a data write mode and a data erase mode, for applying a second voltage to said second conductive film in a selected block including a selected word line, when a first voltage is applied to the selected word line, and for applying a third voltage to said second conductive film in a non-selected block.

Claim 7

A device according to claim 4, wherein in a data read mode, a potential of a selection gate and a drain of a NAND cell is set to a power supply potential, a potential of a word line selected from word lines comprising control gates is set to "1", a potential of non-selected word lines is set to the power supply potential, a potential of a source of said NAND cell is set to "L", and a potential of said substrate is set to "L", thereby setting a potential of said second conductive film to the power supply potential, in a data erase mode, the potential of said selection gate and said drain of said NAND cell is set to "L", the potential of all of said word lines in said NAND cell is set to "L", and the potential of said substrate is set to "L", thereby setting the potential of said second conductive film to "L", or in a data write mode, the potential of said drain of said NAND cell is set to "L" or "M", the potential of said selected word line is set to "L", the potential at a drain-side selection gate and said non-selected word lines is set to "M", and the potential of a source-side selection gate and said substrate is set to "L", thereby setting the potential of said second conductive film to "H".

Claim 8

A device according to claim 6, wherein said NAND cells are divided into blocks each having a plurality of NAND cells, and said second conductive film is formed for said each block, in the data read mode, the potential of said second conductive film in a selected block is set to the power supply potential, the potential of said second conductive film in non-selected blocks is set to "L", in the date write mode, the potential of said second conductive film in said selected block is set to "L", and the potential of said second conductive film in said non-selected blocks is set to "L".

Claim 9

A device according to claim 1, wherein at least two said transistors are connected in series.

Claim 10

A device according to claim 1, further comprising: a plurality of capacitors coupled to the transistors to constitute a plurality of memory cells, in conjunction with the transistor; and bit lines coupled to the transistors.

Claim 11

A device according to claim 9, further comprising voltage supplying means connected to said second conductive film formed on the side surface of the control gate via third insulating film, wherein, when the voltage is applied from said voltage supplying means and for applying a predetermined voltage to said second conductive film.

Claim 12

A device according to claim 10, wherein said bit line formed on the side surface of said second conductive film via the third insulating film and connected to a region to which the inversion layer of said substrate is formed, and said capacitor selectively formed on the side surface of said second conductive film via the third insulating film and connected to another region to which the inversion layer of said substrate is formed.

Claim 13

A device according to claim 9 or 10, wherein one of electrodes constituting said capacitors is formed on the same plane of said first conductive layer.

Claim 14

A device according to claim 9 or 10, wherein one of electrodes constituting said capacitors insulating film.

Claim 15

A device according to claim 9 or 10, wherein one of electrodes constituting said capacitors is formed in a trench selectively formed on said substrate via a fourth insulating film.

Claim 16

A device according to claim 9 or 10, wherein, said transistors are divided into a plurality of blocks and said conductive films are formed for each block, and further comprises: means, in one of a data read mode, a data write mode and a data erase mode, for applying a second voltage to said second conductive film in a selected block including a selected word line, when a first voltage is applied to the selected word line, and for applying a third voltage to said second conductive film in a non-selected block.