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JPH0334380A Expired / Lapsed JP ⏱️ 0.0 years remaining

Semiconductor memory device

Assignee: Panasonic Holdings Corp
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Filing: 1989-06-29
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Granted: —
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Expires: 2009-06-29
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Abstract

Abstract PURPOSE:To make electrons in a floating gate electrically erasable by a method wherein a metal wiring layer is provided so as to envelop the upper parts and the lateral sides of a first and a second gate electrode. CONSTITUTION:A metal wiring layer 8 is made to envelop a first gate electrode 6 and a second gate electrode 7 through the intermediary of an interlaminar insulating film 9. The first gate electrode 6 serves as a floating gate and the second gate electrode 7 serves as a control gate. By applying a voltage to a drain diffusion layer 3 or the control gate 7 and the metal wiring layer 8, photons induced by an avalanche occurred in an Si substrate or electrons emitted between the wiring and the electrodes collide against the metal wiring layer 8 to emit secondary electrons or photons to discharge or neutralize electrons inside the floating gate, so that electrons inside the floating gate can be electrically erased. An ultraviolet erasing device required so far can be dispensed with, and a semiconductor device can be improved without changing cells in area by adding only an upper metal wiring layer.

Inventors

  • 👤 Masaharu Yamamoto
  • 👤 雅晴 山本

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-04 05:07
CPC Classifications
H; H10; H10B; H10B69/00

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