Self-aligned silicide (salicide) process for electrostatic discharge (ESD) protection

Claim 1

A method of forming an integrated circuit having an electrostatic discharge (ESD) protection device, comprising the steps of: providing an internal circuit area and an electrostatic discharge protection area in a semiconductor substrate, wherein each area comprises transistors having a gate and a pair of lightly-doped source and drain regions; forming a dielectric layer over the surface of said semiconductor substrate; forming a photoresist layer over said dielectric layer, said photoresist layer being patterned to cover only said electrostatic discharge protection area; etching said dielectric layer using said photoresist layer as a mask, so to form a sidewall spacer for the gate of said internal circuit area; forming a pair of heavily-doped source and drain regions in said internal circuit area by performing a first ion implantation using said photoresist layer and said sidewall spacer as a mask; forming a metal layer over exposed surfaces of said internal circuit area and said dielectric layer provided on said electrostatic discharge protection area; removing said photoresist layer and a portion of said metal layer over said electrostatic discharge protection area using a lift-off process; removing said dielectric layer over said electrostatic discharge protection area; forming another pair of heavily-doped source and drain regions in said electrostatic discharge protection area by performing a second ion implantation using said gate as a mask; and performing a self-aligned silicide process by annealing said semiconductor substrate.

Claim 2

A method of forming an integrated circuit having an electrostatic discharge (ESD) protection device, comprising the steps of: providing an internal circuit area and an electrostatic discharge protection area in a semiconductor substrate, wherein each area comprises transistors having a gate and a pair of lightly-doped source and drain regions; forming a dielectric layer over the surface of said semiconductor substrate; forming a photoresist layer over said dielectric layer, said photoresist layer being patterned to cover only said electrostatic discharge protection area; etching said dielectric layer using said photoresist layer as a mask, so to form a sidewall spacer for the gate of said internal circuit area; forming a pair of heavily-doped source and drain regions in said internal circuit area by performing a first ion implantation using said photoresist layer and said sidewall spacer as a mask; forming a metal layer over exposed surfaces of said internal circuit area and said dielectric layer provided on said electrostatic discharge protection area; removing said photoresist layer and a portion of said metal layer over said electrostatic discharge protection area using a lift-off process; removing said dielectric layer over said electrostatic discharge protection area; forming another pair of heavily-doped source and drain regions in said electrostatic discharge protection area by performing a second ion implantation using said gate as a mask; and performing a self-aligned silicide process by annealing said semiconductor substrate.