US5374565A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method for ESD protection improvement
Assignee: United Microelectronics Corp
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Filing: 1993-10-22
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Granted: 1994-12-20
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Expires: 2013-10-22
Abstract
Abstract A method of forming an ESD protection device with reduced junction breakdown voltage, simultaneously with an integrated circuit which includes FET devices, and the resultant device structure, are described. A silicon substrate is provided on which there are field oxide regions, gates, and active regions. A first ion implant of a conductivity-imparting dopant is performed in a vertical direction into the active regions of the ESD protection device and the FET devices. A first insulating layer is formed over the ESD protection device and the FET devices, and over the field oxide regions. The first insulating layer is patterned to create spacers adjacent to the gates of both the ESD protection device and the FET devices. A second ion implant of a conductivity-imparting dopant with higher concentration than dopant from the first ion implant is performed into active regions of both the ESD protection device and the FET devices. A second insulating layer is formed over the ESD protection device and the FET devices, and over the field oxide regions. The second insulating layer is patterned to form contact openings to the active regions. Finally, a third ion implant of a conductivity-imparting dopant, with opposite conductivity from the first and second ion implants, having equal concentration to dopant from the first ion implant, is performed through the contact openings into active regions of the ESD protection device.
Inventors
- 👤 Chen-Chiu Hsue
- 👤 Joe Ko
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 16:59
CPC Classifications
H; H10; H10D; H10D89/00; H10D89/60; H10D89/601; H10D89/811
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
224 words
A method of forming an ESD protection device with reduced junction breakdown voltage, simultaneously with an integrated circuit which includes FET devices, on a silicon substrate on which there are field oxide regions, gates, and active regions, comprising the steps of: performing a first ion implant in a vertical direction of a conductivity-imparting dopant into said active regions of the ESD protection device and the FET devices; forming a first insulating layer over said ESD protection device and said FED devices, and over said field oxide regions; patterning said first insulating layer to create spacers adjacent to said gates of both said ESD protection device and said FET devices; performing a second ion implant in a vertical direction of a conductivity-imparting dopant with higher concentration than dopant from said first ion implant, into active regions of both said ESD protection device and said FET devices; forming a second insulating layer over said ESD protection device and said FET devices, and over said field oxide regions; patterning said second insulating layer to form contact openings to said active regions; and performing a third ion implant in a vertical direction of a conductivity-imparting dopant with opposite conductivity from said first and second ion implants, having equal concentration to dopant from said first ion implant, through said contact openings into active regions of said ESD protection device.
Claim 2
Independent Claim
224 words
A method of forming an ESD protection device with reduced junction breakdown voltage, simultaneously with an integrated circuit which includes FET devices, on a silicon substrate on which there are field oxide regions, gates, and active regions, comprising the steps of: performing a first ion implant in a vertical direction of a conductivity-imparting dopant into said active regions of the ESD protection device and the FET devices; forming a first insulating layer over said ESD protection device and said FED devices, and over said field oxide regions; patterning said first insulating layer to create spacers adjacent to said gates of both said ESD protection device and said FET devices; performing a second ion implant in a vertical direction of a conductivity-imparting dopant with higher concentration than dopant from said first ion implant, into active regions of both said ESD protection device and said FET devices; forming a second insulating layer over said ESD protection device and said FET devices, and over said field oxide regions; patterning said second insulating layer to form contact openings to said active regions; and performing a third ion implant in a vertical direction of a conductivity-imparting dopant with opposite conductivity from said first and second ion implants, having equal concentration to dopant from said first ion implant, through said contact openings into active regions of said ESD protection device.
Claim 3
Dependent Claim
30 words
The method of claim 1 wherein said third ion implant is with boron B11 at a dosage of between about 2 E 13 and 2 E 14 atoms/cm. 2 .
Claim 4
Dependent Claim
55 words
The method of claim 2 wherein said first ion implant is with phosphorus P31 at a dosage of between about 1 E 14 and 1 E 15 atoms/cm. 2 , and said second ion implant is with arsenic AS75 at a dosage of between about 1 E 15 and 6 E 15 atoms/cm. 2 .
Claim 5
Dependent Claim
31 words
The method of claim 1 wherein and said third ion implant is with phosphorus P31 at a dosage of between about 2 E 13 and 2 E 14 atoms/cm. 2 .
Claim 6
Dependent Claim
55 words
The method of claim 4 wherein said first ion implant is with boron B11 at a dosage of between about 5 E 12 and 5 E 13 atoms/cm. 2 , and said second ion implant is with boron B11 at a dosage of between about 1 E 15 and 6 E 15 atoms/cm. 2 .
Claim 7
Independent Claim
193 words
A method of forming an ESD protection device with reduced junction breakdown voltage, on a silicon substrate on which there are field oxide regions, gates, and active regions, comprising the steps of: performing a first ion implant in a vertical direction of a conductivity-imparting dopant into said active regions of the ESD protection device; forming a first insulating layer over said ESD protection device and over said field oxide regions; patterning said first insulating layer to create spacers adjacent to said gates of said ESD protection device; performing a second ion implant in a vertical direction of a conductivity-imparting dopant with higher concentration than dopant from said first ion implant, into active regions of said ESD protection device; forming a second insulating layer over said ESD protection device and over said field oxide regions; patterning said second insulating layer to form contact openings to said active regions; and performing a third ion implant in a vertical direction of a conductivity-imparting dopant with opposite conductivity from said first and second ion implants, having equal concentration to dopant from said first ion implant, through said contact openings into active regions of said ESD protection device.
Claim 8
Independent Claim
193 words
A method of forming an ESD protection device with reduced junction breakdown voltage, on a silicon substrate on which there are field oxide regions, gates, and active regions, comprising the steps of: performing a first ion implant in a vertical direction of a conductivity-imparting dopant into said active regions of the ESD protection device; forming a first insulating layer over said ESD protection device and over said field oxide regions; patterning said first insulating layer to create spacers adjacent to said gates of said ESD protection device; performing a second ion implant in a vertical direction of a conductivity-imparting dopant with higher concentration than dopant from said first ion implant, into active regions of said ESD protection device; forming a second insulating layer over said ESD protection device and over said field oxide regions; patterning said second insulating layer to form contact openings to said active regions; and performing a third ion implant in a vertical direction of a conductivity-imparting dopant with opposite conductivity from said first and second ion implants, having equal concentration to dopant from said first ion implant, through said contact openings into active regions of said ESD protection device.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-12-19 | 1998-06-20 | 1998-12-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-12-19 | 2002-06-20 | 2002-12-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-12-19 | 2006-06-20 | 2006-12-20 | $7700.00 | Window Closed / Lapsed |