US5946219A — Method and system for configuring an array of log…

Claim 1

Independent Claim 154 words

A method of configuring a programmable array of logic cells, said array having a plurality of programmable interconnects, each said logic cell having a unique cell location within said array, said array having a logic design associated therewith, the method comprising: accessing a design database representing a configuration of logic cell definitions and interconnections among logic cells corresponding to said logic design; presenting portions of said design database to a user; inputting user specified changes to redefine user selected portions of said design database, including inputting changes to said logic design to change the logical functionality of said logic design; generating a partial configuration bitstream describing only those of said logic cells and said interconnections associated with said redefined portions of said design database; and downloading said partial configuration bitstream into said array of logic cells, thereby configuring only those portions of said array of logic cells which correspond to said user specified changes.

Claim 2

Independent Claim 154 words

A method of configuring a programmable array of logic cells, said array having a plurality of programmable interconnects, each said logic cell having a unique cell location within said array, said array having a logic design associated therewith, the method comprising: accessing a design database representing a configuration of logic cell definitions and interconnections among logic cells corresponding to said logic design; presenting portions of said design database to a user; inputting user specified changes to redefine user selected portions of said design database, including inputting changes to said logic design to change the logical functionality of said logic design; generating a partial configuration bitstream describing only those of said logic cells and said interconnections associated with said redefined portions of said design database; and downloading said partial configuration bitstream into said array of logic cells, thereby configuring only those portions of said array of logic cells which correspond to said user specified changes.

Claim 3

Dependent Claim 28 words

The method of claim 1 wherein said step of generating includes defining said partial configuration bitstream solely on the basis of said redefined portions of said design database.

Claim 4

Dependent Claim 43 words

The method of claim 1 wherein said user specified changes include new logic cell definitions or new interconnections, and said step of generating includes defining said partial configuration bitstream solely on the basis of said new logic cell definitions or said new interconnections.

Claim 5

Dependent Claim 48 words

The method of claim 1 wherein said step of presenting includes identifying certain logic cells which are configured as logic gates, and for each of said certain logic cells displaying a cell location thereof and displaying a graphical image or a textual representation of its corresponding logic gate.

Claim 6

Dependent Claim 44 words

The method of claim 4 wherein said step of inputting user specified changes includes identifying a logic cell to be reconfigured, displaying a list of alternate logic gates and selecting an alternate logic gate from among said list to reconfigure said identified logic cell.

Claim 7

Dependent Claim 25 words

The method of claim 5 wherein said step of displaying a list of alternate logic gates includes displaying graphical representations of said alternate logic gates.

Claim 8

Dependent Claim 85 words

The method of claim 4 wherein said step of presenting further includes: identifying fixed-value logic cells in said design database; for a fixed-value logic cell which is not adjacent to any other fixed-value logic cell, displaying the cell location and the current value of said fixed-value logic cell; and for a group of adjacent fixed-value logic cells, displaying the cell locations of said group as a range of cell locations and displaying the current values of the logic cells in said group as a bitstring.

Claim 9

Dependent Claim 30 words

The method of claim 1 wherein said step of presenting includes displaying only those logic cells which are defined to output a constant logic "1" or a constant logic "0."

Claim 10

Dependent Claim 83 words

The method of claim 1 wherein said step of presenting includes: identifying fixed-value logic cells in said design database; for a fixed-value logic cell which is not adjacent to any other fixed-value logic cell, displaying the cell location and current value of said fixed-value logic cell; for a group of adjacent fixed-value logic cells, displaying the cell locations of said group as a range of cell locations and displaying the current value of each logic cell in said group collectively as a bitstring.

Claim 11

Dependent Claim 203 words

In an FPGA having programmable logic cells and I/O blocks and programmable interconnects disposed between said logic cells and said I/O blocks, a method of generating configuration bitstreams for said FPGA comprising: inputting a logic circuit, said logic circuit including a plurality of logic gates and connections between said logic gates; selecting logic cells and interconnects to implement said logic circuit; forming a design database containing placement and routing information for said selected logic cells and interconnects; generating a first configuration bitstream based on said placement and routing information, said first configuration bitstream containing definitions for all of said selected logic cells and interconnects, thereby implementing said logic circuit; storing said first configuration bitstream in a data store for subsequent downloading into said FPGA; and incorporating changes to the design of said logic circuit; the improvement in the method comprising: displaying portions of said design database to a user and inputting modifications to selected portions of said design database, including inputting changes to said logic circuit to change the logical functionality thereof; and generating a second configuration bitstream containing new definitions only for those of said logic cells and interconnects which relate to said modifications to said selected portions of said design database.

Claim 12

Dependent Claim 203 words

In an FPGA having programmable logic cells and I/O blocks and programmable interconnects disposed between said logic cells and said I/O blocks, a method of generating configuration bitstreams for said FPGA comprising: inputting a logic circuit, said logic circuit including a plurality of logic gates and connections between said logic gates; selecting logic cells and interconnects to implement said logic circuit; forming a design database containing placement and routing information for said selected logic cells and interconnects; generating a first configuration bitstream based on said placement and routing information, said first configuration bitstream containing definitions for all of said selected logic cells and interconnects, thereby implementing said logic circuit; storing said first configuration bitstream in a data store for subsequent downloading into said FPGA; and incorporating changes to the design of said logic circuit; the improvement in the method comprising: displaying portions of said design database to a user and inputting modifications to selected portions of said design database, including inputting changes to said logic circuit to change the logical functionality thereof; and generating a second configuration bitstream containing new definitions only for those of said logic cells and interconnects which relate to said modifications to said selected portions of said design database.

Claim 13

Dependent Claim 18 words

The method of claim 10 further including a step of downloading said first configuration bitstream into said FPGA.

Claim 14

Dependent Claim 28 words

The method of claim 11 further including a step of downloading said second configuration bitstream into said FPGA subsequent to said step of downloading said first configuration bitstream.

Claim 15

Dependent Claim 37 words

The method of claim 10 wherein said step of generating a second configuration bitstream includes defining a bitstream solely on the basis of the locations and new definitions of said those of said logic cells and interconnects.

Claim 16

Dependent Claim 89 words

The method of claim 10 wherein said substep of displaying portions of said design database includes: identifying a first type of logic cells in said design database which are configured as logic gates; for each of said first type of logic cells, displaying its cell location and a representation of its corresponding logic gate; identifying a second type of logic cells in said design database which are configured to produce a constant logic value; and displaying the cell locations and the values of said second type of logic cells.

Claim 17

Dependent Claim 60 words

The method of claim 14 wherein said displaying the cell locations and the values of said second type of logic cells includes forming cell groups containing those of said second type of logic cells which are adjacent to each other, and displaying the cell locations of logic cells in each of said cell groups using a range of cell locations.

Claim 18

Dependent Claim 88 words

The method of claim 15 wherein said substep of forming cell groups includes forming horizontal groups for those of said second type of logic cells which are horizontally adjacent to others of said second type of logic cells, forming vertical groups for those of said second type of logic cells which are vertically adjacent to others of said second type of logic cells, and if a given logic cell belongs to both a horizontal group and a vertical group, assigning said given logic cell to said horizontal group.

Claim 19

Dependent Claim 88 words

The method of claim 15 wherein said substep of forming cell groups includes forming horizontal groups for those of said second type of logic cells which are horizontally adjacent to others of said second type of logic cells, forming vertical groups for those of said second type of logic cells which are vertically adjacent to others of said second type of logic cells, and if a given logic cell belongs to both a horizontal group and a vertical group, assigning said given logic cell to said vertical group.

Claim 20

Dependent Claim 55 words

The method of claim 14 wherein said displaying the cell locations and the values of said second type of logic cells includes forming cell groups which include user specified ones of said second type of logic cells, and displaying the cell locations and the logic values of logic cells in each of said cell groups.

Claim 21

Independent Claim 87 words

A system for configuring an FPGA having at least one logical design programmed therein, comprising: means for detecting conditions external to said FPGA during run-time operation of said FPGA; means for redesigning a portion of said logical design in response to detection of conditions external to said FPGA; means for forming a partial configuration bitstream based solely on said redesigned portion; means for transmitting said partial configuration bitstream to said FPGA, thereby partially reconfiguring said FPGA at run-time to implement said redesigned portion of said logical design.

Claim 22

Independent Claim 87 words

A system for configuring an FPGA having at least one logical design programmed therein, comprising: means for detecting conditions external to said FPGA during run-time operation of said FPGA; means for redesigning a portion of said logical design in response to detection of conditions external to said FPGA; means for forming a partial configuration bitstream based solely on said redesigned portion; means for transmitting said partial configuration bitstream to said FPGA, thereby partially reconfiguring said FPGA at run-time to implement said redesigned portion of said logical design.

Claim 23

Dependent Claim 43 words

The system of claim 19 further including means for storing at least a portion of a design database representative of said logical design, said means for redesigning including means for accessing said design database, thereby providing a basis for redesigning said logical design.

Claim 24

Independent Claim 79 words

A system for configuring an FPGA having at least one logical constant programmed therein, comprising: means for detecting conditions external to said FPGA during run-time operation of said FPGA; means for determining a new value of said logical constant in response to detection of conditions external to said FPGA; means for forming a partial configuration bitstream based solely on said new value; means for transmitting said partial configuration bitstream to said FPGA, thereby partially reconfiguring said FPGA at run-time.

Claim 25

Independent Claim 79 words

A system for configuring an FPGA having at least one logical constant programmed therein, comprising: means for detecting conditions external to said FPGA during run-time operation of said FPGA; means for determining a new value of said logical constant in response to detection of conditions external to said FPGA; means for forming a partial configuration bitstream based solely on said new value; means for transmitting said partial configuration bitstream to said FPGA, thereby partially reconfiguring said FPGA at run-time.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	2002-08-30	2003-03-01	2003-08-31	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	2006-08-30	2007-03-01	2007-08-31	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2010-08-30	2011-03-01	2011-08-31	$7700.00	Window Closed / Lapsed

Method and system for configuring an array of logic devices

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