Method of fabricating a buried reservoir capacitor structure for high-density dynamic random access memory (DRAM) circuits

Claim 1

A method of manufacturing an array of buried reservoir capacitors in a silicon substrate for an array of dynamic random access memory (DRAM) cells comprising the steps of: forming a first photoresist implant mask having an array of openings on said silicon substrate; forming N + doped regions in said silicon substrate in said openings by ion implantation while said first photoresist implant mask prevents ion implantation elsewhere in said silicon substrate; removing said first photoresist implant mask; growing a silicon epitaxy layer on said silicon substrate; forming an array of P-wells in said silicon epitaxy layer over said N + doped regions by using a patterned second photoresist implant mask; removing said second photoresist implant mask; depositing a pad oxide and a silicon nitride layer and forming open areas in said silicon nitride layer in which field oxide isolation regions are required; forming said field oxide isolation regions surrounding and electrically isolating device areas, said device areas aligned over said N + doped regions; anisotropically etching holes in said device areas through said silicon nitride layer and said P-wells in said silicon epitaxy layer to said N + doped regions; isotropically and selectively etching in said holes and thereby removing said N + doped regions, and forming cavities in said silicon substrate; removing said silicon nitride layer by etching; depositing an interelectrode dielectric layer on surface of said cavities and on sidewalls of said holes; depositing a doped polysilicon layer on said interelectrode dielectric layer on said surface of said cavities and filling said holes, said doped polysilicon layer in said holes forming anode electrical contacts for said buried reservoir capacitors; chemical/mechanically polishing back said doped polysilicon layer to surface of said substrate, thereby completing said array of buried reservoir capacitors.

Claim 2

A method of manufacturing an array of buried reservoir capacitors in a silicon substrate for an array of dynamic random access memory (DRAM) cells comprising the steps of: forming a first photoresist implant mask having an array of openings on said silicon substrate; forming N + doped regions in said silicon substrate in said openings by ion implantation while said first photoresist implant mask prevents ion implantation elsewhere in said silicon substrate; removing said first photoresist implant mask; growing a silicon epitaxy layer on said silicon substrate; forming an array of P-wells in said silicon epitaxy layer over said N + doped regions by using a patterned second photoresist implant mask; removing said second photoresist implant mask; depositing a pad oxide and a silicon nitride layer and forming open areas in said silicon nitride layer in which field oxide isolation regions are required; forming said field oxide isolation regions surrounding and electrically isolating device areas, said device areas aligned over said N + doped regions; anisotropically etching holes in said device areas through said silicon nitride layer and said P-wells in said silicon epitaxy layer to said N + doped regions; isotropically and selectively etching in said holes and thereby removing said N + doped regions, and forming cavities in said silicon substrate; removing said silicon nitride layer by etching; depositing an interelectrode dielectric layer on surface of said cavities and on sidewalls of said holes; depositing a doped polysilicon layer on said interelectrode dielectric layer on said surface of said cavities and filling said holes, said doped polysilicon layer in said holes forming anode electrical contacts for said buried reservoir capacitors; chemical/mechanically polishing back said doped polysilicon layer to surface of said substrate, thereby completing said array of buried reservoir capacitors.

Claim 14

A method of manufacturing an array of dynamic random access memory (DRAM) cells having an array of buried reservoir capacitors on and in a silicon substrate comprising the steps of: forming a first photoresist implant mask having an array of openings on said silicon substrate; forming N + doped regions in said silicon substrate in said openings by ion implantation while said first photoresist implant mask prevents ion implantation elsewhere in said silicon substrate; removing said first photoresist implant mask; growing a silicon epitaxy layer on said silicon substrate; forming an array of P-wells in said silicon epitaxy layer over said N + doped regions by using a patterned second photoresist implant mask; removing said second photoresist implant mask; depositing a pad oxide and a silicon nitride layer and forming open areas in said silicon nitride layer in which field oxide isolation regions are required; forming said field oxide isolation regions surrounding and electrically isolating device areas, said device areas aligned over said N + doped regions; anisotropically etching holes in said device areas through said silicon nitride layer and said P-wells in said silicon epitaxy layer to said N + doped regions; isotropically and selectively etching in said holes and thereby removing said N + doped regions, and forming cavities in said silicon substrate; removing said silicon nitride layer by etching; depositing an interelectrode dielectric layer on surface of said cavities and on sidewalls of said holes; depositing a doped polysilicon layer on said interelectrode dielectric layer on said surface of said cavities and filling said holes, said doped polysilicon layer in said holes forming anode electrical contacts for said buried reservoir capacitors; chemical/mechanically polishing back said doped polysilicon layer to surface of said substrate, thereby completing said array of buried reservoir capacitors; and further, forming said array of DRAM cells by, growing a gate oxide on said device areas; depositing and patterning a first polycide layer forming field effect transistor (FET) gate electrodes on said device areas extending over said buried reservoir capacitors, and concurrently forming word lines over said field oxide isolation regions; forming lightly doped source/drain areas adjacent to said gate electrodes by ion implantation; depositing and etching back a conformal insulating layer and forming sidewall spacers on said gate electrodes; forming source/drain contact areas adjacent to said sidewall spacers by ion implantation to form FET access transistors for said array of DRAM cells, one of said source/drain areas of each said transistor extending over one of said anode electrical contacts of said buried reservoir capacitors; depositing and patterning a conducting layer to form a node strap over said interelectrode dielectric layer to form an electrical connection between said source/drain area and said anode electrical contact; depositing a polysilicon/metal dielectric (PMD) layer to insulate said FET gate electrodes and said source/drain areas; etching bit line contact holes in said polysilicon/metal dielectric layer to second of said source/drain areas of each of said FETs; depositing and patterning a second polycide layer to form bit lines extending over and in said bit line contact holes, thereby completing said array of DRAM cells.

Claim 15

A method of manufacturing an array of dynamic random access memory (DRAM) cells having an array of buried reservoir capacitors on and in a silicon substrate comprising the steps of: forming a first photoresist implant mask having an array of openings on said silicon substrate; forming N + doped regions in said silicon substrate in said openings by ion implantation while said first photoresist implant mask prevents ion implantation elsewhere in said silicon substrate; removing said first photoresist implant mask; growing a silicon epitaxy layer on said silicon substrate; forming an array of P-wells in said silicon epitaxy layer over said N + doped regions by using a patterned second photoresist implant mask; removing said second photoresist implant mask; depositing a pad oxide and a silicon nitride layer and forming open areas in said silicon nitride layer in which field oxide isolation regions are required; forming said field oxide isolation regions surrounding and electrically isolating device areas, said device areas aligned over said N + doped regions; anisotropically etching holes in said device areas through said silicon nitride layer and said P-wells in said silicon epitaxy layer to said N + doped regions; isotropically and selectively etching in said holes and thereby removing said N + doped regions, and forming cavities in said silicon substrate; removing said silicon nitride layer by etching; depositing an interelectrode dielectric layer on surface of said cavities and on sidewalls of said holes; depositing a doped polysilicon layer on said interelectrode dielectric layer on said surface of said cavities and filling said holes, said doped polysilicon layer in said holes forming anode electrical contacts for said buried reservoir capacitors; chemical/mechanically polishing back said doped polysilicon layer to surface of said substrate, thereby completing said array of buried reservoir capacitors; and further, forming said array of DRAM cells by, growing a gate oxide on said device areas; depositing and patterning a first polycide layer forming field effect transistor (FET) gate electrodes on said device areas extending over said buried reservoir capacitors, and concurrently forming word lines over said field oxide isolation regions; forming lightly doped source/drain areas adjacent to said gate electrodes by ion implantation; depositing and etching back a conformal insulating layer and forming sidewall spacers on said gate electrodes; forming source/drain contact areas adjacent to said sidewall spacers by ion implantation to form FET access transistors for said array of DRAM cells, one of said source/drain areas of each said transistor extending over one of said anode electrical contacts of said buried reservoir capacitors; depositing and patterning a conducting layer to form a node strap over said interelectrode dielectric layer to form an electrical connection between said source/drain area and said anode electrical contact; depositing a polysilicon/metal dielectric (PMD) layer to insulate said FET gate electrodes and said source/drain areas; etching bit line contact holes in said polysilicon/metal dielectric layer to second of said source/drain areas of each of said FETs; depositing and patterning a second polycide layer to form bit lines extending over and in said bit line contact holes, thereby completing said array of DRAM cells.