CMOS processing employing separate spacers for independently optimized transistor performance

Claim 1

A method of manufacturing a CMOS semiconductor device comprising an N-channel transistor and P-channel transistor, which method comprises sequentially: forming a dielectric layer on a surface of a semiconductor substrate; forming a conductive layer on the dielectric layer; patterning the conductive layer to form a first gate electrode of the N-channel transistor and a second gate electrode of the P-channel transistor, each gate electrode having an upper surface and side surfaces; using the first gate electrode as a mask, implanting impurities to form N-type lightly doped implants in the semiconductor substrate; forming first insulating sidewall spacers on the side surfaces of the first and second gate electrodes; using the first gate electrode and first insulating sidewall spacers as a mask, implanting impurities to form N-type moderately doped or heavily doped implants in the semiconductor substrate; activation annealing at a first temperature to form source/drain regions of the N-channel transistor comprising N-type lightly doped and moderately or heavily doped portions, the lightly doped portions extending below the surface of the semiconductor substrate to a first depth and the N-type moderately or heavily doped portions extending below the surface of the semiconductor substrate to a second depth greater than the first depth; using the second gate electrode and first insulating sidewall spacers as a mask, ion implanting impurities to form P-type lightly doped implants in the semiconductor substrate; forming second insulating sidewall spacers on the first insulating sidewall spacers on the side surfaces of the second gate electrode; using the second gate electrode and first and second insulating sidewall spacers thereon as a mask, implanting impurities to form P-type moderately or heavily doped implants in the semiconductor substrate; and activation annealing at a second temperature to form source/drain regions of the P-channel transistor comprising P-type lightly doped and moderately or heavily doped portions, the P-type lightly doped portions extending below the semiconductor substrate to a third depth and the P-type moderately or heavily doped portions extending below the semiconductor substrate to a fourth depth greater than the third depth.

Claim 2

A method of manufacturing a CMOS semiconductor device comprising an N-channel transistor and P-channel transistor, which method comprises sequentially: forming a dielectric layer on a surface of a semiconductor substrate; forming a conductive layer on the dielectric layer; patterning the conductive layer to form a first gate electrode of the N-channel transistor and a second gate electrode of the P-channel transistor, each gate electrode having an upper surface and side surfaces; using the first gate electrode as a mask, implanting impurities to form N-type lightly doped implants in the semiconductor substrate; forming first insulating sidewall spacers on the side surfaces of the first and second gate electrodes; using the first gate electrode and first insulating sidewall spacers as a mask, implanting impurities to form N-type moderately doped or heavily doped implants in the semiconductor substrate; activation annealing at a first temperature to form source/drain regions of the N-channel transistor comprising N-type lightly doped and moderately or heavily doped portions, the lightly doped portions extending below the surface of the semiconductor substrate to a first depth and the N-type moderately or heavily doped portions extending below the surface of the semiconductor substrate to a second depth greater than the first depth; using the second gate electrode and first insulating sidewall spacers as a mask, ion implanting impurities to form P-type lightly doped implants in the semiconductor substrate; forming second insulating sidewall spacers on the first insulating sidewall spacers on the side surfaces of the second gate electrode; using the second gate electrode and first and second insulating sidewall spacers thereon as a mask, implanting impurities to form P-type moderately or heavily doped implants in the semiconductor substrate; and activation annealing at a second temperature to form source/drain regions of the P-channel transistor comprising P-type lightly doped and moderately or heavily doped portions, the P-type lightly doped portions extending below the semiconductor substrate to a third depth and the P-type moderately or heavily doped portions extending below the semiconductor substrate to a fourth depth greater than the third depth.