Memory device having a plurality of cell array blocks including reference cells are connected in series

Claim 2

A memory device comprising: a first cell block comprising a plurality of cells, a first bit line being electrically connected to a selected one of the cells; a second cell block comprising a plurality of cells, a second bit line being electrically connected to a predetermined number of cells, greater than one, which are connected in series; and a comparator for comparing a first signal received from the first bit line to a second signal received from the second bit line to determine a bit data of the selected cell.

Claim 3

The memory device according to claim 1, wherein the predetermined number is determined so that the second signal is set to a signal level between an on level and an off level of the first signal which correspond to a 1 and a 0 of the bit data of the selected cell, respectively.

Claim 4

The memory device according to claim 1, wherein the first and second cell blocks are formed from a common circuit pattern including a plurality of transistors.

Claim 5

The memory device according to claim 1, wherein the comparator comprises: a first converter for converting a first current flowing through the first bit line to a first voltage; a second converter for converting a second current flowing through the second bit line to a second voltage; and a differential amplifier for amplifying a difference between the first and second voltages to produce the bit data of the selected cell.

Claim 6

The memory device according to claim 1, wherein the first and second cell blocks include diffused contacts and the number of the diffused contacts in the first cell block is equal to the number of the diffused contacts in the second cell block.

Claim 7

The memory device according to claim 5, wherein the selected cell is connected to the first bit line through one of the diffused contacts of the first cell block.

Claim 8

The memory device according to claim 5, wherein the serially connected cells are connected to the second bit line through one of the diffused contacts of the second cell block.

Claim 9

The memory device according to claim 1, wherein a capacitance of the bit line for the first cell block is approximately equal to a capacitance of the bit line for the second cell block.

Claim 10

The memory device according to claim 1, wherein a charging speed of the bit line for the first cell block is approximately equal to a charging speed of the bit line for the second cell block.

Claim 11

The memory device according to claim 9, wherein the predetermined number is determined so that the second signal is set to a signal level between an on level and an off level of the first signal which correspond to a 1 and a 0 of the bit data of the selected cell, respectively.

Claim 12

A memory device comprising: a plurality of first cell blocks each comprising a plurality of cells and a first bit line contact which is selectively connected to one of the plurality of cells, a predetermined number of first cell blocks being connected to a first bit line through the first bit line contacts thereof; a plurality of second cell blocks each comprising a plurality of cells and a second bit line contact, a predetermined number of second cell blocks being connected to a second bit line through the second bit line contacts thereof, wherein a predetermined cell block of the plurality of second cell blocks includes a reference element which is formed with a plurality of cells connected in series, the reference element being connected to the second bit line through the second bit line contact of the predetermined cell block; and a comparator for comparing a first signal received from the first bit line to a second signal received from the second bit line to determine a bit data of the selectively connected cell.

Claim 13

A memory device comprising: a plurality of first cell blocks each comprising a plurality of cells and a first bit line contact which is selectively connected to one of the plurality of cells, a predetermined number of first cell blocks being connected to a first bit line through the first bit line contacts thereof; a plurality of second cell blocks each comprising a plurality of cells and a second bit line contact, a predetermined number of second cell blocks being connected to a second bit line through the second bit line contacts thereof, wherein a predetermined cell block of the plurality of second cell blocks includes a reference element which is formed with a plurality of cells connected in series, the reference element being connected to the second bit line through the second bit line contact of the predetermined cell block; and a comparator for comparing a first signal received from the first bit line to a second signal received from the second bit line to determine a bit data of the selectively connected cell.

Claim 14

The memory device according to claim 11, wherein the first and second cell blocks are formed from a common circuit pattern including a plurality of transistors.

Claim 15

The memory device according to claim 11, wherein the comparator comprises: a first converter for converting a first current flowing through the first bit line to a first voltage; a second converter for converting a second current flowing through the second bit line to a second voltage; and a differential amplifier for amplifying a difference between the first and second voltages to produce the bit data of the selected cell.

Claim 16

The memory device according to claim 11, wherein the predetermined number of the first cell blocks is equal to the predetermined number of the second cell blocks.

Claim 17

The memory device according to claim 14, wherein the number of cells of the reference element is determined so that the reference signal is set to a signal level between an on level and an off level of the cell signal which correspond to a 1 and a 0 of the bit data of the selected cell, respectively.

Claim 18

The memory device according to claim 14, wherein the first signal is transmitted from the selectively connected cell.

Claim 19

A memory device comprising: a plurality of cell blocks arranged in rows and columns and having bit lines for columns, respectively, each cell block comprising a plurality of cells and a bit line contact which is selectively connected to a cell through a selector according to address data, cell blocks in each column being connected to a bit line through bit line contacts thereof; a bit line selector for selecting one of the bit lines according to the address data; and a sense amplifier for amplifying a difference between a reference signal and a cell signal received from the selectively connected cell through the selected bit line to produce a bit data of the selectively connected cell, wherein the cell blocks include a reference cell block which includes a reference element comprising a plurality of cells connected in series, the reference element being connected to a reference bit line corresponding to the reference cell block through a bit line contact thereof.

Claim 20

A memory device comprising: a plurality of cell blocks arranged in rows and columns and having bit lines for columns, respectively, each cell block comprising a plurality of cells and a bit line contact which is selectively connected to a cell through a selector according to address data, cell blocks in each column being connected to a bit line through bit line contacts thereof; a bit line selector for selecting one of the bit lines according to the address data; and a sense amplifier for amplifying a difference between a reference signal and a cell signal received from the selectively connected cell through the selected bit line to produce a bit data of the selectively connected cell, wherein the cell blocks include a reference cell block which includes a reference element comprising a plurality of cells connected in series, the reference element being connected to a reference bit line corresponding to the reference cell block through a bit line contact thereof.

Claim 21

The memory device according to claim 17, wherein the reference cell block and the other cell blocks are formed from a common circuit pattern including a plurality of transistors.

Claim 22

The memory device according to claim 17, wherein the comparator comprises: a first converter for converting a cell current flowing through the selected bit line to a cell voltage; a second converter for converting a reference current flowing through the reference bit line to a reference voltage; and a differential amplifier for amplifying a difference between the cell voltage and the reference voltage to produce the bit data of the selected cell.

Claim 23

The memory device according to claim 17, wherein the second signal is received from the second bit line.

Claim 24

The memory device according to claim 20, wherein a capacitance of the selected bit line is approximately equal to a capacitance of the reference bit line.

Claim 25

The memory device according to claim 20, wherein a charging speed of the selected bit line is approximately equal to a charging speed of the reference bit line.