Read-only memory

Claim 2

A read-only memory comprising: a plurality of source lines to be supplied with a predetermined potential; a plurality of data lines alternately and parallelly disposed with said source lines; a plurality of word lines, together disposed along a plane in an orthogonal direction with respect to said plurality of data and source lines above the surface of a semiconductor substrate; a plurality of MOSFETs for forming individual memory cells each of which has a gate coupled to an associated word line, a source region coupled to one of said source lines at one of a plurality of electrical contact locations there at and a drain region coupled to one of said data lines at one of a plurality of electrical contact locations thereat such that with respect to each source line electrical contact location which is used for coupling with a MOSFET source region, the source region of four MOSFETs are coupled thereto and the drain regions thereof are coupled to different electrical contact locations on the adjacent data lines, on either side of an associated source line, thereby effecting a repeating arrangement of four MOSFETs displayed in a criss-cross pattern and wherein one of said MOSFETs has a first threshold voltage which is different from that of said other MOSFETs; a plurality of depletion type MOSFETs respectively coupled between a first node and said plurality of data lines, each depletion type MOSFET having its gate supplied with a predetermined first potential so that the potential level of an associated data line is controllably limited to a predetermined second potential which is lower than a third potential to be supplied to said first node; and a potential supplying means coupled to said first node for selectively supplying said third potential level to said first node in response to a control signal.

Claim 3

A read-only memory according to claim 1, wherein said potential supplying means includes a switching circuit supplied with said third potential and a fourth potential, different from said third potential, and being responsive to said control signal for selectively supplying one of said third and fourth potentials to said first node.

Claim 4

A read-only memory according to claim 2, wherein said third potential is a power supply potential and said fourth potential and said predetermined potential are ground potential.

Claim 5

A read-only memory according to claim 2, wherein the individual gate electrodes of the memory cell MOSFETs are integrally formed with an associated word line and that each arrangement of said four MOSFETs is associated with an adjacent pair of word lines and a pair of data lines having interposed therebetween a source line functioning as a common source line for the four MOSFETs.

Claim 6

A read-only memory according to claim 4, wherein said word lines are individually directioned to effect a zig-zag pattern including sections which intersect at underlying portions thereof both said alternately disposed data and source lines at substantially right angles and wherein said zig-zag pattern is such that alternately disposed word lines remain substantially from each other throughout their entire length.

Claim 7

A read-only memory according to claim 1, wherein the individual gate electrodes of the memory cell MOSFETs are integrally formed with an associated word line and that each arrangement of said four MOSFETs is associated with an adjacent pair of word lines and a pair of data lines having interposed therebetween a source line functioning as a common source line for the four MOSFETs.

Claim 8

A read-only memory according to claim 6, wherein said word lines are individually directioned to effect a zig-zag pattern including section which intersect at underlying portions thereof both said alternately disposed data and source lines at substantially right angles and wherein said zig-zag pattern is such that alternately disposed word lines remain substantially equidistant from each other throughout their entire length.

Claim 9

A read-only memory according to claim 1, wherein a second plurality of depletion type MOSFETs are respectively coupled between said first node and said source lines, the gates thereof being supplied with said predetermined potential, and wherein said first node supplying means is coupled to said plurality of source lines for selectively providing said predetermined potential to a source line.

Claim 10

A read-only memory comprising: a plurality of source lines to be supplied with a predetermined potential; a plurality of data lines alternately and parallelly disposed with said source lines; a plurality of word lines, together disposed along a plane in an orthogonal direction with respect to said plurality of data and source lines above the surface of a semiconductor substrate; a plurality of MOSFETs for forming individual memory cells each of which has a gate coupled to an associated word line, a source region coupled to one of said source lines at one of a plurality electrical contact locations thereat and a drain region coupled to one of said data lines at one of a plurality of electrical contact locations thereat such that with respect to each source line electrical contact location which is used for coupling with a MOSFET source region, the source region of four MOSFETs are coupled thereto and the drain regions thereof are coupled to different electrical contact locations on the adjacent data lines, on either side of an associated source line, thereby effecting a repeating arrangement of four MOSFETs disposed in a criss-cross pattern and wherein one of said MOSFETs has a first threshold voltage which is different from that of said other MOSFETs; a plurality of depletion type MOSFETs respectively coupled between a first node and said plurality of data lines, each depletion type MOSFET having its gate supplied with said predetermined potential so that the potential level of an associated data line is controllably limited to a predetermined second potential which is lower than a third potential to be supplied to said first node; a first supplying means coupled to said first node for selectively supplying said third potential level to said first node in response to a control signal; a dummy cell array including a dummy data line, a plurality of word lines intersecting said dummy data line, a plurality of dummy memory cells respectively provided at intersections between associated word lines and said dummy data line, and a depletion type MOSFET coupled between a second node supplied with a fourth potential and said dummy data line, the gate thereof being supplied with a predetermined potential so as to controllably limit the potential attained at said dummy data line to a predetermined potential lower in magnitude than said fourth potential; second supplying means coupled to said second node and being responsive to said control signal for selectively supplying said fourth potential to said second node; first selecting means coupled to said plurality of data lines for selecting a data line; and amplifier means having inputs selectively coupled to both a data line and to said dummy data line during a read-out operation, wherein data on said data line representative of a selected memory cell is sensed.

Claim 11

A read-only memory comprising: a plurality of source lines to be supplied with a predetermined potential; a plurality of data lines alternately and parallelly disposed with said source lines; a plurality of word lines, together disposed along a plane in an orthogonal direction with respect to said plurality of data and source lines above the surface of a semiconductor substrate; a plurality of MOSFETs for forming individual memory cells each of which has a gate coupled to an associated word line, a source region coupled to one of said source lines at one of a plurality electrical contact locations thereat and a drain region coupled to one of said data lines at one of a plurality of electrical contact locations thereat such that with respect to each source line electrical contact location which is used for coupling with a MOSFET source region, the source region of four MOSFETs are coupled thereto and the drain regions thereof are coupled to different electrical contact locations on the adjacent data lines, on either side of an associated source line, thereby effecting a repeating arrangement of four MOSFETs disposed in a criss-cross pattern and wherein one of said MOSFETs has a first threshold voltage which is different from that of said other MOSFETs; a plurality of depletion type MOSFETs respectively coupled between a first node and said plurality of data lines, each depletion type MOSFET having its gate supplied with said predetermined potential so that the potential level of an associated data line is controllably limited to a predetermined second potential which is lower than a third potential to be supplied to said first node; a first supplying means coupled to said first node for selectively supplying said third potential level to said first node in response to a control signal; a dummy cell array including a dummy data line, a plurality of word lines intersecting said dummy data line, a plurality of dummy memory cells respectively provided at intersections between associated word lines and said dummy data line, and a depletion type MOSFET coupled between a second node supplied with a fourth potential and said dummy data line, the gate thereof being supplied with a predetermined potential so as to controllably limit the potential attained at said dummy data line to a predetermined potential lower in magnitude than said fourth potential; second supplying means coupled to said second node and being responsive to said control signal for selectively supplying said fourth potential to said second node; first selecting means coupled to said plurality of data lines for selecting a data line; and amplifier means having inputs selectively coupled to both a data line and to said dummy data line during a read-out operation, wherein data on said data line representative of a selected memory cell is sensed.

Claim 12

A read-only memory according to claim 9, wherein each one of said word lines in said dummy memory array physically corresponds to an individual word line commonly associated with a group of said memory cells.

Claim 13

A read-only memory according to claim 10, wherein each said first and second supplying means includes a switching circuit supplied with said third potential and said fourth potential, respectively, on the one hand, and a fifth potential, different from said third and fourth potentials, on the other hand, said third and fourth potentials having a same potential value, said switching circuit is responsive to said control signal for selectively supplying concurrently the same one of said third and fifth potentials to said first and second nodes; and wherein said depletion type MOSFETs coupled to said data lines and that one coupled to said dummy data line have a same predetermined potential bias voltage applied at the respective gates thereof.

Claim 14

A read-only memory according to claim 11, wherein said amplifier means includes a first and second depletion type MOSFET, each having a gate biased at said predetermined potential and a source-to-drain current path and an amplifier circuit having a first input node selectively coupled to a data line via the source-to-drain current path of said first depletion type MOSFET and having a second input node coupled to the dummy data line via the source-to-drain current path of said second depletion type MOSFET.

Claim 15

A read-only memory cell according to claim 12, wherein said dummy memory array further includes said dummy data line and which dummy data line is parallelly interposed between a pair of dummy source lines and wherein each dummy cell includes at least two MOSFETs, the source-to-drain current path of a first one of said two MOSFETs is coupled between said dummy data line and said predetermined potential and has said first threshold voltage and the source-to-drain current path of the second one of said two MOSFETs is coupled in parallel to the source-to-drain current path of said first MOSFET and has a threshold voltage different from said first threshold voltage.

Claim 16

A read-only memory cell according to claim 13, wherein in said dummy memory array the source-to-drain current path of said first MOSFET is coupled between said dummy data line and one of said pair of dummy source lines and said second MOSFET is coupled between said dummy data line and the other one of said pair of dummy source lines, said dummy source lines become grounded during the sensing operation.

Claim 17

A read-only memory cell according to claim 10, wherein said dummy memory array further includes said dummy data line and which dummy data line is parallelly interposed between a pair of dummy source lines and wherein each dummy cell includes at least two MOSFETs, the source-to-drain current path of a first one of said two MOSFETs is coupled between said dummy data line and said predetermined potential and has said first threshold voltage and the source-to-drain current path of the second one of said two MOSFETs is coupled in parallel to the source-to-drain current path of said first MOSFET and has a threshold voltage different from said first threshold voltage.

Claim 18

A read-only memory cell according to claim 15, wherein in said dummy memory array the source-to-drain current path of said first MOSFET is coupled between said dummy data line and one of said pair of dummy source lines and said second MOSFET is coupled between said dummy data line and the other one of said pair of dummy source lines, said dummy source lines become grounded during the sensing operation.

Claim 19

A read-only memory according to claim 9, wherein each said first and second supplying means includes a switching circuit supplied with said third potential and said fourth potential, respectively, on the one hand, and a fifth potential, different from said third and fourth potentials, on the other hand, said third and fourth potentials having a same potential value, said switching circuit is responsive to said control signal for selectively supplying concurrently the same one of said third and fourth potentials to said first and second nodes; and wherein said depletion tube MOSETs coupled to said data lines and that one coupled to said dummy data line have a same predetermined potential bias voltage applied at the respective gates thereof.

Claim 20

A read-only memory according to claim 17, wherein said amplifier means includes a first and second depletion type MOSFET, each having a gate biased at said predetermined potential and a source-to-drain current path, and an amplifier circuit having a first input node selectively coupled to a data line via the source-to-drain current path of said first depletion type MOSFET and having a second input node coupled to the dummy data line via the source-to-drain current path of said second depletion type MOSFET.

Claim 21

A read-only memory cell according to claim 18, wherein said dummy memory array further includes said dummy data line and which dummy data line is parallelly interposed between a pair of dummy source lines and wherein each dummy cell includes at least two MOSFETs, the source-to-drain current path of a first one of said two MOSFETs is coupled between said dummy data line and said predetermined potential and has said first threshold voltage and the source-to-drain current path of the second one of said two MOSFETs is coupled in parallel to the source-to-drain current path of said first MOSFET and has a threshold voltage different from said first threshold voltage.

Claim 22

A read-only memory cell according to claim 19, wherein in said dummy memory array the source-to-drain current path of said first MOSFET is coupled between said dummy data line and one of said pair of dummy source lines and said second MOSFET is coupled between said dummy data line and the other one of said pair of dummy source lines, said dummy source lines become grounded during the sensing operation.

Claim 23

A read-only memory cell according to claim 9, wherein said dummy memory array further includes said dummy data and which dummy data line is parallelly interposed between a pair of dummy source lines and wherein each dummy dell includes at least two MOSFETs, the source-to-drain current path of a first one of said two MOSFETs is coupled between said dummy data line and said predetermined potential and has said first threshold voltage and the source-to-drain current path of the second one of said two MOSFETs is coupled in parallel to the source-to-drain current path of said first MOSFET and ha a threshold voltage different from said first threshold voltage.

Claim 24

A read-only memory cell according to claim 21, wherein in said dummy memory array the source-to-drain current path of said first MOSFET is coupled between said dummy data line and one of said pair of dummy source lines and said second MOSFET is coupled between said dummy data line and the other one of said pair of dummy source lines, said dummy source lines become grounded during the sensing operation.

Claim 25

A read-only memory according to claim 9, wherein a second plurality of depletion type MOSFETs are respectively coupled between said first node and said source lines, the gates thereof being supplied with said predetermined potential, and wherein said first node supplying means is coupled to said plurality of source lines for selectively providing said predetermined potential to a source line.

Claim 26

A read-only memory according to claim 9, wherein said word lines are individually directioned to effect a zig-zag pattern including sections which intersect at underlaying portions thereof both said alternately disposed data and source lines at substantially right angles and wherein said zig-zag pattern is such that alternately disposed word lines remain substantially equidistant from each other throughout their entire length.