US4933906A
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US
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Non-volatile semiconductor memory device
Assignee: Mitsubishi Electric Corp
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Filing: 1988-11-18
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Granted: 1990-06-12
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Expires: 2008-11-18
Abstract
Abstract A semiconductor memory device of erasable programmable rear only memory type is disclosed the memory device has a pair of memory cell arrays between which a differential amplifier is provided. Each of the memory cell arrays has a current-to-voltage converter circuit associated therewith. When a memory cell in either one of the pair of memory cell array is selected, a bit line being coupled to the selected memory cell is charged by one current-voltage conversion circuit, while at the same time at least one bit line in the other memory cell array where no memory cell has been selected is charged by the associated current-voltage converter circuit at arrayed different from the bit line coupled to the selected memory cell. A differential amplifier senses and amplifies a potential difference between the charged bit lines to provide a high speed read-out of the memory device.
Inventors
- 👤 Yasushi Terada
- 👤 Takeshi Nakayama
- 👤 Kazuo Kobayashi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 05:09
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/26; G11C16/28
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
283 words
A non-volatile semiconductor memory device comprising: a plurality of erasable programmable memory cells arranged into a pair of memory cell arrays, each memory cell being coupled to one of a plurality of bit lines and one of a plurality of word lines; address input means for providing a bit line select signal and a word line select signal for selecting a particular memory cell in either of said memory cell arrays; a first voltage supply means for applying a first predetermined voltage on the bit line coupled to the memory cell to be selected in one of said memory cell arrays upon the selection of said memory cell; a second voltage supply means for applying a second predetermined voltage on at least one bit line in the memory cell array not including the selected memory cell simultaneously with the application of said first predetermined voltage on said bit line by said first voltage supply means; a first current-to-voltage converter means for converting a current flow through said bit line caused by the application of the first predetermined voltage by said first voltage supply means into a corresponding first output signal voltage; a second current-to-voltage converter means for converting a current flow through said bit line caused by the application of the second predetermined voltage by said second voltage supply means into a corresponding second output signal voltage; means for differentiating the rates at which the first and second output signal voltages of said respective first and second current-to-voltage converter means change; and means for detecting the voltage difference between the first and second output signal voltages of said first and second current-to-voltage converter means and producing a data output signal in response thereto.
Claim 2
Dependent Claim
283 words
A non-volatile semiconductor memory device comprising: a plurality of erasable programmable memory cells arranged into a pair of memory cell arrays, each memory cell being coupled to one of a plurality of bit lines and one of a plurality of word lines; address input means for providing a bit line select signal and a word line select signal for selecting a particular memory cell in either of said memory cell arrays; a first voltage supply means for applying a first predetermined voltage on the bit line coupled to the memory cell to be selected in one of said memory cell arrays upon the selection of said memory cell; a second voltage supply means for applying a second predetermined voltage on at least one bit line in the memory cell array not including the selected memory cell simultaneously with the application of said first predetermined voltage on said bit line by said first voltage supply means; a first current-to-voltage converter means for converting a current flow through said bit line caused by the application of the first predetermined voltage by said first voltage supply means into a corresponding first output signal voltage; a second current-to-voltage converter means for converting a current flow through said bit line caused by the application of the second predetermined voltage by said second voltage supply means into a corresponding second output signal voltage; means for differentiating the rates at which the first and second output signal voltages of said respective first and second current-to-voltage converter means change; and means for detecting the voltage difference between the first and second output signal voltages of said first and second current-to-voltage converter means and producing a data output signal in response thereto.
Claim 3
Dependent Claim
31 words
A non-volatile semiconductor memory device according to claim 1 wherein said differentiating means comprises means for accelerating the change of the first output signal voltage from said first current-to-voltage converter means.
Claim 4
Dependent Claim
41 words
A non-volatile semiconductor memory device according to claim 2 wherein said accelerating means comprises a third voltage supply means responsive to an externally applied address signal to provide a predetermined voltage on the bit line coupled to said selected memory cell.
Claim 5
Dependent Claim
54 words
A non-volatile semiconductor memory device according to claim 3 wherein said third voltage supply means comprises; a voltage supply having a predetermined voltage level, and a first switching means connected between said voltage supply and said bit line coupled to said selected memory cell and operable in response to an externally applied address signal.
Claim 6
Dependent Claim
31 words
A non-volatile semiconductor memory device according to claim 1 wherein said differentiating means comprises means for decelerating the change of the first output signal voltage from said second current-to-voltage converter means.
Claim 7
Dependent Claim
42 words
A non-volatile semiconductor memory device according to claim 5 wherein said decelerating means comprises; ground potential means, and capacitance means to be connected between said ground potential means and said at least one bit line associated with said non-selected memory cell array.
Claim 8
Dependent Claim
21 words
A non-volatile semiconductor memory device according to claim 1 wherein said means for detecting the voltage difference comprises a differential amplifier.
Claim 9
Dependent Claim
26 words
A non-volatile semiconductor memory device according to claim 1 wherein said first and second current-to-voltage converter means include said first and second voltage supply means, respectively.
Claim 10
Dependent Claim
26 words
A non-volatile semiconductor memory device according to claim 1 wherein said memory cells included in said memory cell arrays comprise erasable programmable read only memory cells.
Claim 11
Dependent Claim
25 words
A non-volatile semiconductor memory device according to claim 9 wherein said erasable programmable read only memory cells comprise electrically erasable programmable read only memory cells.
Claim 12
Dependent Claim
147 words
An improved reading circuit for a memory in which data is stored in a form which is sensed as different impedance values, representing distinct values of said data, and which is divided into at least two selectable portions and including selecting means for selecting one of said selectable portions, said reading circuit comprising: means for providing current to each of said selectable portions, said current providing means presenting a predetermined impedance to said current and including means for presenting reduced impedance to one of said selectable portions in response to said selecting means, current-to-voltage conversion means, responsive to said current providing means for converting the value of current provided thereby to a voltage and differential voltage amplifying means responsive to voltages produced by said current-to-voltage conversion means for producing an output indicating the difference in current flowing to said selected portion and at least one non-selected portion.
Claim 13
Dependent Claim
147 words
An improved reading circuit for a memory in which data is stored in a form which is sensed as different impedance values, representing distinct values of said data, and which is divided into at least two selectable portions and including selecting means for selecting one of said selectable portions, said reading circuit comprising: means for providing current to each of said selectable portions, said current providing means presenting a predetermined impedance to said current and including means for presenting reduced impedance to one of said selectable portions in response to said selecting means, current-to-voltage conversion means, responsive to said current providing means for converting the value of current provided thereby to a voltage and differential voltage amplifying means responsive to voltages produced by said current-to-voltage conversion means for producing an output indicating the difference in current flowing to said selected portion and at least one non-selected portion.
Claim 14
Dependent Claim
201 words
A reading circuit for a memory having selectable memory cells presenting distinct resistive impedances in dependence on the value of data stored therein, when selected, said memory being divided into at least two selectable portions, each presenting a parasitic load, said memory further including portion selection means for selecting one of said selectable portions and memory cell selection means for selecting a memory cell in a portion of said memory selected by said portion selection means, said reading circuit comprising: current supply means for supplying current to each of said memory portions and presenting a predetermined resistive impedance to said current, said current supply means including means for presenting a reduced series impedance to said current supplied to a selected portion of said memory in response to said selection means; reset means for selectively connecting each of said selectable portions to a reference potential and disconnecting said selectable portion therefrom; and differential amplifier means for amplifying the difference between a voltage produced at a node between said reduced impedance and the resistive impedance presented by a selected memory cell and a voltage produced at a node between said series impedance and said parasitic load of a non-selected portion of said memory.
Claim 15
Dependent Claim
201 words
A reading circuit for a memory having selectable memory cells presenting distinct resistive impedances in dependence on the value of data stored therein, when selected, said memory being divided into at least two selectable portions, each presenting a parasitic load, said memory further including portion selection means for selecting one of said selectable portions and memory cell selection means for selecting a memory cell in a portion of said memory selected by said portion selection means, said reading circuit comprising: current supply means for supplying current to each of said memory portions and presenting a predetermined resistive impedance to said current, said current supply means including means for presenting a reduced series impedance to said current supplied to a selected portion of said memory in response to said selection means; reset means for selectively connecting each of said selectable portions to a reference potential and disconnecting said selectable portion therefrom; and differential amplifier means for amplifying the difference between a voltage produced at a node between said reduced impedance and the resistive impedance presented by a selected memory cell and a voltage produced at a node between said series impedance and said parasitic load of a non-selected portion of said memory.
Claim 16
Independent Claim
143 words
A method of reading data from a memory including a plurality of selectable memory cells by sensing of impedance of a selected one of said memory cells, wherein the memory is divided into at least two selectable portions, each of said selectable portions having at least one said selectable memory cells, said selectable portions presenting a parasitic load and wherein said memory includes means for applying a current to each of said selectable portions through a predetermined impedance comprising the steps of: connecting each of said selectable blocks to a source of reference potential; decreasing said predetermined impedance to a selected one of said selectable blocks; disconnecting each of said selectable blocks from said source of reference potential; and sensing a differential voltage between a node of a selected portion containing a selected memory cell and a corresponding node of a non-selected portion.
Claim 17
Independent Claim
143 words
A method of reading data from a memory including a plurality of selectable memory cells by sensing of impedance of a selected one of said memory cells, wherein the memory is divided into at least two selectable portions, each of said selectable portions having at least one said selectable memory cells, said selectable portions presenting a parasitic load and wherein said memory includes means for applying a current to each of said selectable portions through a predetermined impedance comprising the steps of: connecting each of said selectable blocks to a source of reference potential; decreasing said predetermined impedance to a selected one of said selectable blocks; disconnecting each of said selectable blocks from said source of reference potential; and sensing a differential voltage between a node of a selected portion containing a selected memory cell and a corresponding node of a non-selected portion.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-06-11 | 1993-12-11 | 1994-06-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-06-11 | 1997-12-11 | 1998-06-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-06-11 | 2001-12-11 | 2002-06-12 | $7700.00 | Window Closed / Lapsed |