US5937324A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method for forming a line-on-line multi-level metal interconnect structure for use in integrated circuits
Assignee: NXP USA Inc
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Filing: 1998-03-13
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Granted: 1999-08-10
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Expires: 2018-03-13
Abstract
Abstract A method of manufacturing a semiconductor component with a multi-level interconnect system includes providing a substrate (11), fabricating a device (12) in the substrate (11), forming an interconnect layer (15) over the substrate (11), depositing a dielectric layer (20) over the interconnect layer (15), depositing a separate interconnect layer (21) over the dielectric layer (20), etching a via (31) in the separate interconnect layer (21) and in the dielectric layer (20), and depositing a different interconnect layer (40) over the separate interconnect layer (21) and in the via (31) wherein the another interconnect layer (40) electrically couples the interconnect layer (15) and the separate interconnect layer (21).
Inventors
- 👤 David A. Abercrombie
- 👤 Rickey S. Brownson
- 👤 Michael R. Cherniawski
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 18:30
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/40; H10W20/41; H10W20/435; H10W20/01; H10W20/031; H10W20/069; H10W20/0693; H10W20/071; H10W20/074; H10W20/076; H10W20/081; H10W20/083; H10W20/42; H10W20/425
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
206 words
A method of manufacturing a semiconductor component comprising: providing a semiconductor substrate; fabricating a semiconductor device in the semiconductor substrate; forming a first interconnect layer over the semiconductor substrate; depositing a first dielectric layer over the first interconnect layer; polishing the first dielectric layer to result in planarization of a top surface of the first dielectric layer; depositing a second interconnect layer over the first dielectric layer; forming a first etch mask over the second interconnect layer; etching a via in the second interconnect layer wherein the via in the second interconnect layer is defined by the first etch mask and wherein the via in the second interconnect layer exposes a portion of the first dielectric layer; extending the via into the first dielectric layer after etching the via in the second interconnect layer wherein the via in the second interconnect layer exposes the via in the first dielectric layer and the portion of the first interconnect layer; removing the first etch mask from the second interconnect layer; and depositing a third interconnect layer over the second interconnect layer and in the vias of the first dielectric layer and the second interconnect layer wherein the third interconnect layer electrically couples the first and second interconnect layers.
Claim 2
Independent Claim
206 words
A method of manufacturing a semiconductor component comprising: providing a semiconductor substrate; fabricating a semiconductor device in the semiconductor substrate; forming a first interconnect layer over the semiconductor substrate; depositing a first dielectric layer over the first interconnect layer; polishing the first dielectric layer to result in planarization of a top surface of the first dielectric layer; depositing a second interconnect layer over the first dielectric layer; forming a first etch mask over the second interconnect layer; etching a via in the second interconnect layer wherein the via in the second interconnect layer is defined by the first etch mask and wherein the via in the second interconnect layer exposes a portion of the first dielectric layer; extending the via into the first dielectric layer after etching the via in the second interconnect layer wherein the via in the second interconnect layer exposes the via in the first dielectric layer and the portion of the first interconnect layer; removing the first etch mask from the second interconnect layer; and depositing a third interconnect layer over the second interconnect layer and in the vias of the first dielectric layer and the second interconnect layer wherein the third interconnect layer electrically couples the first and second interconnect layers.
Claim 3
Dependent Claim
21 words
The method of claim 1 further comprising: depositing as the third interconnect layer, a layer that comprises a refractory metal component.
Claim 4
Dependent Claim
96 words
The method of claim 2 wherein the step of etching the via in the second interconnect layer includes providing the via in the second interconnect layer with a sidewall and wherein the step of etching the via in the first dielectric layer includes providing the via in the first dielectric layer with a sidewall and wherein the step of depositing the third interconnect layer includes physically contacting the third interconnect layer with the portion of the first interconnect layer and with the sidewalls of the vias in the first dielectric layer and the second interconnect layer.
Claim 5
Dependent Claim
30 words
The method of claim 2 further comprising: forming a second etch mask over the third interconnect layer; and patterning the second and third interconnect layers with the second etch mask.
Claim 6
Dependent Claim
153 words
The method of claim 4 wherein the step of patterning the second and third interconnect layers includes providing a substantially equal width for a first portion of the second interconnect layer, a second portion of the second interconnect layer, a first portion of the third interconnect layer, and a second portion of the third interconnect layer wherein the first portion of the third interconnect layer is located in and adjacent to the vias of the second interconnect layer and the first dielectric layer and wherein the first portion of the second interconnect layer is located adjacent to the vias of the second interconnect layer and the first dielectric layer and wherein the second portion of the second interconnect layer is located adjacent to the first portion of the second interconnect layer and wherein the second portion of the third interconnect layer is located adjacent to the first portion of the third interconnect layer.
Claim 7
Dependent Claim
81 words
The method of claim 2 further comprising: providing an electrically conductive layer below the first interconnect layer; depositing a second dielectric layer into the via of the first dielectric layer; and etching the second dielectric layer to expose a portion of the via of the first dielectric layer and the portion of the first interconnect layer wherein the second dielectric layer prevents the second interconnect layer from physically contacting the electrically conductive layer through the via of the first dielectric layer.
Claim 8
Dependent Claim
25 words
The method of claim 2 wherein the step of depositing the third interconnect layer includes providing a refractory anti-reflective material for the third interconnect layer.
Claim 9
Dependent Claim
142 words
The method of claim 1 further comprising: removing the first etch mask from the second interconnect layer; depositing a second dielectric layer over the second interconnect layer after the step of etching the via in the first dielectric layer; etching a via in the second dielectric layer to expose a portion of the second interconnect layer; depositing a third dielectric layer in the via of the second dielectric layer; etching the third dielectric layer to expose a portion of the via in the second dielectric layer and to expose the portion of the second interconnect layer; and depositing a third interconnect layer in the portion of the via of the second dielectric layer, the third interconnect layer electrically coupled to the portion of the second interconnect layer, the third dielectric layer electrically isolating the third interconnect layer and the first interconnect layer.
Claim 10
Dependent Claim
54 words
The method of claim 8 wherein the step of etching the via in the second interconnect layer includes defining a width of the portion of the second interconnect layer wherein a width of the via in the second dielectric layer is approximately equal to the width of the portion of the second interconnect layer.
Claim 11
Dependent Claim
17 words
The method of claim 2 further comprising forming the third interconnect layer as an anti-reflective coating layer.
Claim 12
Independent Claim
141 words
A method for forming a semiconductor structure, the method comprising the steps of: forming a first conductive layer; forming an inter-level dielectric layer over the first conductive layer; forming a second conductive layer overlying the inter-level dielectric layer; removing first portions of the second conductive layer to expose alignment marks; using the alignment marks to define a position of a contact opening through the second conductive layer and the inter-level dielectric layer to expose a contact port ion of the first conductive layer; forming a third conductive layer which electrically contacts both the second conductive layer the contact portion of the first conductive layer, the second and third conductive layers forming a composite interconnect layer; and masking and etching the composite interconnect layer to form an interconnect structure which is electrically connected to the contact portion of the first conductive layer.
Claim 13
Independent Claim
141 words
A method for forming a semiconductor structure, the method comprising the steps of: forming a first conductive layer; forming an inter-level dielectric layer over the first conductive layer; forming a second conductive layer overlying the inter-level dielectric layer; removing first portions of the second conductive layer to expose alignment marks; using the alignment marks to define a position of a contact opening through the second conductive layer and the inter-level dielectric layer to expose a contact port ion of the first conductive layer; forming a third conductive layer which electrically contacts both the second conductive layer the contact portion of the first conductive layer, the second and third conductive layers forming a composite interconnect layer; and masking and etching the composite interconnect layer to form an interconnect structure which is electrically connected to the contact portion of the first conductive layer.
Claim 14
Independent Claim
225 words
A method for manufacturing a semiconductor component, the method comprising the steps of: providing a semiconductor substrate; forming a plurality of semiconductor devices in the semiconductor substrate; forming a first interconnect layer over the semiconductor substrate, the first interconnect layer electrically coupled to the plurality of semiconductor devices; forming a first dielectric layer overlying the first interconnect layer, the first dielectric layer having a via exposing a portion of the first interconnect layer the via having a contact dimension; forming a second interconnect layer overlying a portion of the first dielectric layer, the second interconnect layer devoid of physical contact with the first interconnect layer, the second interconnect layer having a via exposing the via of the first dielectric layer and exposing the portion of the first interconnect layer; and forming a third interconnect layer overlying the second interconnect layer and the first interconnect layer, a first portion of the third interconnect layer located in the via of the second interconnect layer and located in the via of the first dielectric layer, the third interconnect layer electrically coupling the second interconnect layer and the first interconnect layer through the via of the first dielectric layer and through the via of the second interconnect layer wherein a lithographic width of the second interconnect layer and the third interconnect layer is substantially equal to the contact dimension.
Claim 15
Independent Claim
225 words
A method for manufacturing a semiconductor component, the method comprising the steps of: providing a semiconductor substrate; forming a plurality of semiconductor devices in the semiconductor substrate; forming a first interconnect layer over the semiconductor substrate, the first interconnect layer electrically coupled to the plurality of semiconductor devices; forming a first dielectric layer overlying the first interconnect layer, the first dielectric layer having a via exposing a portion of the first interconnect layer the via having a contact dimension; forming a second interconnect layer overlying a portion of the first dielectric layer, the second interconnect layer devoid of physical contact with the first interconnect layer, the second interconnect layer having a via exposing the via of the first dielectric layer and exposing the portion of the first interconnect layer; and forming a third interconnect layer overlying the second interconnect layer and the first interconnect layer, a first portion of the third interconnect layer located in the via of the second interconnect layer and located in the via of the first dielectric layer, the third interconnect layer electrically coupling the second interconnect layer and the first interconnect layer through the via of the first dielectric layer and through the via of the second interconnect layer wherein a lithographic width of the second interconnect layer and the third interconnect layer is substantially equal to the contact dimension.
Claim 16
Dependent Claim
14 words
The method of claim 12 wherein the plurality of semiconductor devices are bipolar transistors.
Claim 17
Dependent Claim
19 words
The method of claim 12 wherein the first dielectric layer is planarized by a chemical mechanical polishing (CMP) process.
Claim 18
Dependent Claim
18 words
The semiconductor component of claim 12 wherein the third interconnect layer comprises one of either tungsten or titanium.
Claim 19
Dependent Claim
23 words
The semiconductor component of claim 12 wherein the third interconnect layer a composite refractory metal layer containing a plurality of refractory metallic atoms.
Claim 20
Dependent Claim
33 words
The semiconductor component of claim 12 wherein the third interconnect layer functions as both an electrical interconnect material between the first and second interconnect layers and as an anti-reflective coating for lithographic operations.
Claim 21
Dependent Claim
33 words
The semiconductor component of claim 12 wherein the third interconnect layer functions as both an electrical interconnect material between the first and second interconnect layers and as an anti-reflective coating for lithographic operations.
Claim 22
Dependent Claim
38 words
The semiconductor component of claim 12 wherein the third interconnect layer has a bottom portion of titanium that is between 200-400 Angstroms in thickness and an upper portion of titanium nitride that is between 400-1000 Angstroms in thickness.
Claim 23
Dependent Claim
16 words
The semiconductor component of claim 12 wherein a dielectric sidewall spacer is formed within the via.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-08-09 | 2003-02-08 | 2003-08-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-08-09 | 2007-02-08 | 2007-08-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-08-09 | 2011-02-08 | 2011-08-10 | $7700.00 | Window Closed / Lapsed |