Silicon carbide power MESFET with surface effect supressive layer

Claim 2

A field effect transistor comprising: a silicon carbide substrate; a silicon carbide n+ type channel layer positioned adjacent to said substrate; a pair of silicon carbide n+ regions spaced apart and positioned adjacent to said channel layer; a source contact affixed to one of said pair of n+ regions; a drain contact affixed to the other of said pair of n+ regions; a gate contact positioned adjacent to said channel layer intermediate said pair of n+ regions; said channel layer being subject to an undesired surface current; a surface-effect-suppressive layer which covers portions of a surface of said channel layer between said gate contact and each of said n+ regions and being operable to alter said portions of said surface in a manner to substantially minimize the effects of said undesired surface current; the space above said surface-effect-suppressive layer defining respective gaps, on either side of said gate contact, said gaps being devoid of said surface-effect-suppressive layer; and wherein said gate contact is superposed directly on said channel layer, and said field effect transistor is a MESFET; and wherein said surface effect suppressive layer is formed on and is substantially coextensive with said channel layer except at said gate contact, and wherein said spaced apart n+ regions are formed upon said surface effect suppressive layer.

Claim 3

The field effect transistor of claim 1 wherein said surface-effect-suppressive layer is undoped silicon carbide.

Claim 4

A field effect transistor comprising: a silicon carbide substrate; a silicon carbide n+ type channel layer positioned adjacent to said substrate; a pair of silicon carbide n+ regions spaced apart and positioned adjacent to said channel layer; a source contact affixed to one of said pair of n+ regions; a drain contact affixed to the other of said pair of n+ regions; a gate contact positioned adjacent to said channel layer intermediate said pair of n+ regions; said channel layer being subject to an undesired surface current; a surface-effect-suppressive layer which covers portions of a surface of said channel layer between said gate contact and each of said n+ regions and being operable to alter said portions of said surface in a manner to substantially minimize the effects of said undesired surface current; the space above said surface-effect-suppressive layer defining respective gaps, on either side of said gate contact, said gaps being devoid of said surface-effect-suppressive layer; and wherein said gate contact is superposed directly on said channel layer, and said field effect transistor is a MESFET; said surface-effect-suppressive layer is a silicon dioxide insulator and is formed upon and covers at least a portion of each of said spaced apart n+ regions except at said source contact and said drain contact, and said surface-effect-suppressive layer is generally coextensive with said channel layer except at said gate contact; and wherein said silicon dioxide is comprised of a combination of thermally grown silicon dioxide and chemical-vapor-deposition-formed silicon dioxide.

Claim 5

A field effect transistor comprising: a silicon carbide substrate; a silicon carbide n+ type channel layer positioned adjacent to said substrate; a pair of silicon carbide n+ regions spaced apart and positioned adjacent to said channel layer; a source contact affixed to one of said pair of n+ regions; a drain contact affixed to the other of said pair of n+ regions; a gate contact positioned adjacent to said channel layer intermediate said pair of n+ regions; said channel layer being subject to an undesired surface current; a surface-effect-suppressive layer which covers portions of a surface of said channel layer between said gate contact and each of said n+ regions and being operable to alter said portions of said surface in a manner to substantially minimize the effects of said undesired surface current; the space above said surface-effect-suppressive layer defining respective gaps, on either side of said gate contact, said gaps being devoid of said surface-effect-suppressive layer; and wherein said gate contact is superposed directly on said channel layer, and said field effect transistor is a MESFET; said surface-effect-suppressive layer is a silicon dioxide insulator and is formed upon and covers at least a portion of each of said spaced apart n+ regions except at said source contact and said drain contact, and said surface-effect-suppressive layer is generally coextensive with said channel layer except at said gate contact; and wherein said silicon dioxide is comprised of a combination of thermally grown silicon dioxide and chemical-vapor-deposition-formed silicon dioxide.

Claim 6

The transistor of claim 3 wherein said surface-effect-suppressive layer has a thickness between about 500 and 5000 Angstroms.

Claim 7

The transistor of claim 3 wherein said surface-effect-suppressive layer has a thickness of about 2000 Angstroms.

Claim 8

A field effect transistor comprising: a silicon carbide substrate; a silicon carbide n type channel layer positioned adjacent to said substrate; a pair of silicon carbide n+ regions spaced apart and positioned adjacent to said channel layer; a source contact affixed to one of said pair of n+ regions; a drain contact affixed to the other of said pair of n+ regions; a gate contact positioned adjacent to said channel layer intermediate said pair of n+ regions; said channel layer being subject to an undesired surface current; a surface-effect-suppressive layer which covers portions of a surface of said channel layer between said gate contact and each of said n+ regions and being operable to alter said portions of said surface in a manner to substantially minimize the effects of said undesired surface current; the space above said surface-effect-suppressive layer defining respective gaps, on either side of said gate contact, said gaps being devoid of said surface-effect-suppressive layer; and wherein a p+ silicon carbide region is interposed between said gate contact and said channel layers, and said field effect transistor is a JFET.

Claim 9

A field effect transistor comprising: a silicon carbide substrate; a silicon carbide n type channel layer positioned adjacent to said substrate; a pair of silicon carbide n+ regions spaced apart and positioned adjacent to said channel layer; a source contact affixed to one of said pair of n+ regions; a drain contact affixed to the other of said pair of n+ regions; a gate contact positioned adjacent to said channel layer intermediate said pair of n+ regions; said channel layer being subject to an undesired surface current; a surface-effect-suppressive layer which covers portions of a surface of said channel layer between said gate contact and each of said n+ regions and being operable to alter said portions of said surface in a manner to substantially minimize the effects of said undesired surface current; the space above said surface-effect-suppressive layer defining respective gaps, on either side of said gate contact, said gaps being devoid of said surface-effect-suppressive layer; and wherein a p+ silicon carbide region is interposed between said gate contact and said channel layers, and said field effect transistor is a JFET.

Claim 10

A field effect transistor comprising: a silicon carbide substrate; a silicon carbide n type channel layer positioned adjacent to said substrate; a pair of silicon carbide n+ regions spaced apart and positioned adjacent to said channel layer; a source contact affixed to one of said pair of n+ regions; a drain contact affixed to the other of said pair of n+ regions; a gate contact positioned adjacent to said channel layer intermediate said pair of n+ regions; said channel layer being subject to an undesired surface current; a surface-effect-suppressive layer which covers portions of a surface of said channel layer between said gate contact and each of said n+ regions and being operable to alter said portions of said surface in a manner to substantially minimize the effects of said undesired surface current; the space above said surface-effect-suppressive layer defining respective gaps, on either side of said gate contact, said gaps being devoid of said surface-effect-suppressive layer; and wherein a silicon dioxide is interposed between said gate contact and said channel layer, and said field effect transistor is a MOSFET.

Claim 11

A field effect transistor comprising: a silicon carbide substrate; a silicon carbide n type channel layer positioned adjacent to said substrate; a pair of silicon carbide n+ regions spaced apart and positioned adjacent to said channel layer; a source contact affixed to one of said pair of n+ regions; a drain contact affixed to the other of said pair of n+ regions; a gate contact positioned adjacent to said channel layer intermediate said pair of n+ regions; said channel layer being subject to an undesired surface current; a surface-effect-suppressive layer which covers portions of a surface of said channel layer between said gate contact and each of said n+ regions and being operable to alter said portions of said surface in a manner to substantially minimize the effects of said undesired surface current; the space above said surface-effect-suppressive layer defining respective gaps, on either side of said gate contact, said gaps being devoid of said surface-effect-suppressive layer; and wherein a silicon dioxide is interposed between said gate contact and said channel layer, and said field effect transistor is a MOSFET.