← Back to Patent Explorer
US5043777A Expired / Lapsed US ⏱️ 0.0 years remaining

Power FETS with improved high voltage performance

Assignee: Micron Technology Inc
•
Filing: 1990-09-28
•
Granted: 1991-08-27
•
Expires: 2010-09-28
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract An undoped surface layer over and lattice matched to the n-channel layer between the gate contact and the spaced apart source and drain n+ regions in power FETs made of group III-V compounds minimizes surface effects that preclude such devices from operating efficiently at high voltages, and improves reliability. The undoped surface layer may be grown on the n-channel layer before the layer forming the n+ regions, or where the n+ regions can be formed in the undoped surface layer. The invention is especially suitable for GaAs MESFETs and HEMTs.

Inventors

  • 👤 Saptharishi Sriram

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-29 15:50
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/40; H10D30/47; H10D30/471; H10D30/475; H10D30/4755; H10D30/80; H10D30/801

Claims Analysis

Total Claims: 24
Claim 1
Independent Claim 111 words
A field effect transistor comprising: a substrate; an n-channel layer on said substrate; a pair of n+ regions spaced apart by a portion of said n-channel layer; a source contact affixed to one of said n+ regions; a drain contact affixed to the other n+ region; an undoped surface layer covering said n-channel layer at least between said n+ regions, said undoped layer being lattice matched to the n-channel layer and having a thickness of at least about 1000 angstroms to substantially reduce surface resistivity effects of said n-channel layer; and a gate contact extending through said undoped surface layer and contacting said n-channel layer between the spaced apart n+ regions.
Claim 2
Dependent Claim 111 words
A field effect transistor comprising: a substrate; an n-channel layer on said substrate; a pair of n+ regions spaced apart by a portion of said n-channel layer; a source contact affixed to one of said n+ regions; a drain contact affixed to the other n+ region; an undoped surface layer covering said n-channel layer at least between said n+ regions, said undoped layer being lattice matched to the n-channel layer and having a thickness of at least about 1000 angstroms to substantially reduce surface resistivity effects of said n-channel layer; and a gate contact extending through said undoped surface layer and contacting said n-channel layer between the spaced apart n+ regions.
Claim 3
Dependent Claim 25 words
The field effect transistor of claim 1 wherein said substrate, n-channel layer, n+ regions, and undoped surface layer all consist essentially of group III-V compounds.
Claim 4
Dependent Claim 41 words
The field effect transistor of claim 2 wherein said undoped surface layer is grown on and is substantially coextensive with said n-channel layer except at said gate contact, and wherein said spaced apart n+ regions are grown on said undoped layer.
Claim 5
Dependent Claim 19 words
The field effect transistor of claim 3 wherein said undoped surface layer is about 1000 to 5000 angstroms thick.
Claim 6
Dependent Claim 17 words
The field effect transistor of claim 4 wherein said undoped surface layer is about 2000 angstrom thick.
Claim 7
Dependent Claim 30 words
The field effect transistor of claim 2 wherein said undoped surface layer is grown over the n-channel layer and said spaced apart n+ regions are formed in said undoped layer.
Claim 8
Dependent Claim 19 words
The field effect transistor of claim 6 wherein said undoped surface layer is about 1000 to 5000 angstroms thick.
Claim 9
Dependent Claim 17 words
The field effect transistor of claim 7 wherein said undoped surface layer is about 2000 angstroms thick.
Claim 10
Dependent Claim 15 words
The field effect transistor of claim 2 wherein said field effect transistor is a MESFET.
Claim 11
Dependent Claim 14 words
The field effect transistor of claim 9 wherein said group III-V comopound is GaAs.
Claim 12
Dependent Claim 19 words
The field effect transistor of claim 10 wherein said undoped surface layer is about 1000 to 5000 angstroms thick.
Claim 13
Dependent Claim 17 words
The field effect transistor of claim 11 wherein said undoped surface layer is about 2000 angstroms thick.
Claim 14
Dependent Claim 46 words
The field effect transistor of claim 11 wherein said undoped surface layer is grown on and is substantially coextensive with said free surface of said n-channel layer except at said gate contact, and wherein said spaced apart n+ regions are grown on said undoped surface layer.
Claim 15
Dependent Claim 30 words
The field effect transistor of claim 11 wherein said undoped surface layer is grown over the n-channel layer and said spaced apart n+ regions are formed in said undoped layer.
Claim 16
Dependent Claim 18 words
The field effect transistor of claim 2 wherein said field effect transistor is a high mobility electron transistor.
Claim 17
Dependent Claim 19 words
The field effect transistor of claim 15 wherein said undoped surface layer is about 1000 to 5000 angstroms thick.
Claim 18
Dependent Claim 17 words
The field effect transistor of claim 16 wherein said undoped surface layer is about 2000 angstroms thick.
Claim 19
Dependent Claim 25 words
The field effect transistor of claim 15 wherein said substrate, n-channel layer, n+ regions, and undoped surface layer all consist essentially of group III-V compounds.
Claim 20
Dependent Claim 44 words
The field effect transistor of claim 18 wherein said group III-V compounds for said n+ regions said substrate and said undoped surface layer comprise GaAs and wherein said n-channel includes an undoped GaAs layer, a doped GaAs layer and an aluminum gallium arsenide layer.
Claim 21
Dependent Claim 105 words
A field effect transistor comprising: a substrate; a GaAs n-channel layer on said substrate; a pair of n+ regions spaced apart by a portion of said n-channel layer; a source contact affixed to one of said n+ regions; a drain contact affixed to the other n+ region; an undoped GaAs surface layer covering said n-channel layer at least between said n+ regions, said undoped layer having a thickness of at least about 1000 angstroms to substantially reduce surface resistivity effects of said n-channel layer; and a gate contact extending through said undoped surface layer and contacting said n-channel layer between the spaced apart n+ regions.
Claim 22
Dependent Claim 105 words
A field effect transistor comprising: a substrate; a GaAs n-channel layer on said substrate; a pair of n+ regions spaced apart by a portion of said n-channel layer; a source contact affixed to one of said n+ regions; a drain contact affixed to the other n+ region; an undoped GaAs surface layer covering said n-channel layer at least between said n+ regions, said undoped layer having a thickness of at least about 1000 angstroms to substantially reduce surface resistivity effects of said n-channel layer; and a gate contact extending through said undoped surface layer and contacting said n-channel layer between the spaced apart n+ regions.
Claim 23
Dependent Claim 20 words
The field effect transistor of claim 20 wherein said undoped GaAs surface layer is about 1000 to 5000 Å thick.
Claim 24
Dependent Claim 17 words
The field effect transistor of claim 3 wherein said undoped GaAs layer is about 200 Å thick.

References Cited (Backward Citations)

US4641161A Cited
US4916498A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1994-08-26 1995-02-25 1995-08-27 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1998-08-26 1999-02-25 1999-08-27 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2002-08-26 2003-02-25 2003-08-27 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag