US5923872A
Expired / Lapsed
US
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Apparatus for sampling instruction operand or result values in a processor pipeline
Assignee: Hewlett Packard Development Co LP
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Filing: 1997-11-26
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Granted: 1999-07-13
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Expires: 2017-11-26
Abstract
Abstract An apparatus is provided for sampling values of operands of instructions in a processor pipeline of a system, the pipeline having a plurality of processing stages. Instructions are fetched into a first stage of the pipeline. Any one of the fetched instructions are identified as a particular selected instruction. Values of results computed during the processing of the particular selected instruction are recorded in a sampling record along with state information identifying the particular selected instruction. Software is informed whenever the particular selected instruction leaves the pipeline to read the recorded values and state information.
Inventors
- 👤 George Z. Chrysos
- 👤 Jeffrey Dean
- 👤 James E. Hicks
- 👤 Carl A. Waldspurger
- 👤 William E. Weihl
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 14:50
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/30; G06F11/34; G06F11/3466; G06F11/348
Claims Analysis
Total Claims: 34
Claim 1
Independent Claim
94 words
An apparatus for sampling values of operands of instructions in a processor pipeline of a system, the pipeline having a plurality of processing stages, comprising: means for fetching instructions into a first stage of the pipeline; means for identifying any one of the fetched instructions as a particular selected instruction; means for recording result values of operands computed during the processing of the particular selected instruction; means for recording state information identifying the particular selected instruction; and means for informing software whenever the particular selected instruction leaves the pipeline to read the recorded values.
Claim 2
Independent Claim
94 words
An apparatus for sampling values of operands of instructions in a processor pipeline of a system, the pipeline having a plurality of processing stages, comprising: means for fetching instructions into a first stage of the pipeline; means for identifying any one of the fetched instructions as a particular selected instruction; means for recording result values of operands computed during the processing of the particular selected instruction; means for recording state information identifying the particular selected instruction; and means for informing software whenever the particular selected instruction leaves the pipeline to read the recorded values.
Claim 3
Dependent Claim
11 words
The apparatus of claim 1 wherein the instructions are selected randomly.
Claim 4
Dependent Claim
20 words
The apparatus of claim 1 wherein the operands and results include values stored in registers accessed by the selected instruction.
Claim 5
Dependent Claim
18 words
The apparatus of claim 1 wherein the operands include values of memory locations accessed by the selected instruction.
Claim 6
Dependent Claim
19 words
The apparatus of claim 1 wherein the operands include intermediate values computed during the execution of the selected instruction.
Claim 7
Dependent Claim
12 words
The apparatus of claim 5 wherein the intermediate values include effective addresses.
Claim 8
Dependent Claim
18 words
The apparatus of claim 1 wherein the operand values are recorded prior to executing the particular selected instruction.
Claim 9
Dependent Claim
18 words
The apparatus of claim 1 wherein the operand values are recorded after the particular selected instruction completes execution.
Claim 10
Dependent Claim
22 words
The apparatus of claim 1 wherein the means for informing software generates an interrupt when the particular selected instruction leaves the pipeline.
Claim 11
Dependent Claim
34 words
The apparatus of claim 1 wherein the means for informing software sets a flag that can be polled by the software, the flag to indicate that the particular selected instruction has left the pipeline.
Claim 12
Dependent Claim
15 words
The apparatus of claim 1 wherein the state information includes addresses of the selected instruction.
Claim 13
Dependent Claim
17 words
The apparatus of claim 1 wherein the state information includes identification of processes executing the selected instructions.
Claim 14
Dependent Claim
13 words
The apparatus of claim 1 wherein the state information includes address space numbers.
Claim 15
Dependent Claim
14 words
The apparatus of claim 1 wherein the state information includes a hardware context identifier.
Claim 16
Dependent Claim
20 words
The apparatus of claim 1 wherein operand values and state information for multiple potentially concurrently executing selected instructions are sampled.
Claim 17
Dependent Claim
15 words
The apparatus of claim 6 wherein the effective addresses are virtual memory addresses of data.
Claim 18
Dependent Claim
15 words
The apparatus of claim 6 wherein the effective addresses are virtual memory addresses of instructions.
Claim 19
Dependent Claim
14 words
The apparatus of claim 6 wherein the effective addresses are physical addresses of data.
Claim 20
Dependent Claim
14 words
The apparatus of claim 6 wherein the effective addresses are physical addresses of instructions.
Claim 21
Dependent Claim
13 words
The apparatus of claim 1 wherein the state information includes a thread identifier.
Claim 22
Independent Claim
88 words
A method for sampling values of operands of instructions in a processor pipeline, the pipeline having a plurality of processing stages, comprising: fetching instructions into a first stage of the pipeline; identifying any one of the fetched instructions as a particular processing of the particular selected instruction; recording result values of operands computed during the processing of the particular selected instructions; recording state information identifying the particular selected instructions; and informing software whenever the particular instruction leaves the pipeline to read the recorded result values and state information.
Claim 23
Independent Claim
88 words
A method for sampling values of operands of instructions in a processor pipeline, the pipeline having a plurality of processing stages, comprising: fetching instructions into a first stage of the pipeline; identifying any one of the fetched instructions as a particular processing of the particular selected instruction; recording result values of operands computed during the processing of the particular selected instructions; recording state information identifying the particular selected instructions; and informing software whenever the particular instruction leaves the pipeline to read the recorded result values and state information.
Claim 24
Dependent Claim
11 words
The method of claim 21, wherein the instructions are selected randomly.
Claim 25
Dependent Claim
31 words
The method of claim 21, wherein the operands include one of values of memory locations accessed by the selected instructions and intermediate values computed during the execution of the selected instruction.
Claim 26
Dependent Claim
20 words
The method of claim 21, wherein the operands are recorded prior to or after the particular selected instruction completes execution.
Claim 27
Dependent Claim
28 words
The method of claim 21, wherein the state information is one of addresses of selected information, identification of processes executing the selected instructions, and a hardware context identifier.
Claim 28
Dependent Claim
13 words
The method of claim 21, wherein the state information is a thread identifier.
Claim 29
Dependent Claim
12 words
The method of claim 21, wherein the intermediate values include effective addresses.
Claim 30
Dependent Claim
27 words
The method of claim 27, wherein effective addresses are one of (i) virtual memory addresses of data or instructions or (ii) physical addresses of data or instruction.
Claim 31
Dependent Claim
14 words
The method of claim 21, wherein two or more executing selected instructions are sampled.
Claim 32
Dependent Claim
22 words
The method of claim 21, wherein the step of informing software generates an interrupt when the particular selected instruction leaves the pipeline.
Claim 33
Dependent Claim
22 words
The method of claim 21, wherein the operands and the result valves include values stored in registers accessed by the selected instructions.
Claim 34
Dependent Claim
33 words
The method of claim 21, wherein the step of informing software sets a flag that can be polled by the software, the flag indicating that the particular selected instruction has left the pipeline.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-07-12 | 2003-01-11 | 2003-07-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-07-12 | 2007-01-11 | 2007-07-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-07-12 | 2011-01-11 | 2011-07-13 | $7700.00 | Window Closed / Lapsed |