Synchronous DRAM including an output data latch circuit being controlled by burst address

Claim 1

A SDRAM of a semiconductor memory element which comprises: a plurality of memory cell arrays which are made of a plurality of cells being selected by an address and storing data, rows and columns; a plurality of row and column decoders for selecting the rows and the columns; a bit line sense-amplifier and a data bus line sense-amplifier which amplify a cell data selected by the address after the cell data is sequentially loaded on a bit line and a data bus line during a read operation; a data output buffer which performs a buffering operation with the data of the data bus line and outputs a result to the outside after the data of the data bus line is transmitted to a global Input/Output (GIO) line, further comprising: a mode register for programming a burst length; a column address buffer and latch means controlling the operation of the column decoder by a column active signal; a burst length counter means which generates a burst address as long as a programmed burst length to the mode register after receiving a burst start address; a burst control means for controlling the burst length counter means; and a data latch means which temporarily stores the data transmitted to the global I/O line, and transmits the stored data to the data output buffer by controlling the burst address.