US5703830A
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Syncronous dynamic semiconductor memory device using pipelined multi-bit prefetch architecture
Assignee: Longitude Semiconductor SARL
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Filing: 1996-08-23
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Granted: 1997-12-30
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Expires: 2016-08-23
Abstract
Abstract In a synchronous dynamic semiconductor memory device, a plurality of data paths, each of which is formed by a column decoder, a sense amplifier and a first-stage data amplifier, are provided between a column address buffer having a burst counter function and a second-stage data amplifier which is further connected to a data latch circuit.
Inventors
- 👤 Takai Yasuhiro
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 20:38
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C7/00; G11C7/10; G11C7/1072
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
337 words
A synchronous dynamic semiconductor memory device comprising: a column address buffer including burst counters and generating first and second series of address signals in synchronization with every two clock cycles of a clock signal; a first column decoder, connected to said column address buffer, for decoding said first series of address signals in synchronization with every two clock cycles of said clock signal; a second column decoder, connected to said column address buffer, for decoding said second series of address signals in synchronization with every two clock cycles of said clock signal; a first sense amplifier, connected to said first column decoder, for amplifying a first data signal in accordance with a first column switch signal of said first column decoder and generating a voltage at a first read bus; a second sense amplifier, connected to said second column decoder, for amplifying a second data signal in accordance with a second column switch signal of said second column decoder and generating a voltage at a second read bus; a first first-stage data amplifier, connected to said first read bus, for amplifying the voltage of said first read bus and transmitting an amplified voltage of said first read bus to a read/write bus in synchronization with every two clock cycles of said clock signal; a second first-stage data amplifier, connected to said second read bus, for amplifying the voltage of said second read bus and transmitting an amplified voltage of said second read bus to said read/write bus in synchronization with every two clock cycles of said clock signal, said second first-stage data amplifier being operated time-divisionally with said first first-stage data amplifier; a second-stage data amplifier, connected to said read/write bus, for amplifying a voltage of said read/write bus in synchronization with every one clock cycle of said clock signal; and a data latch circuit, connected to said second-stage data amplifier, for latching an output of said second-stage data amplifier in synchronization with every one clock cycle of said clock signal to generate an output data signal.
Claim 2
Dependent Claim
337 words
A synchronous dynamic semiconductor memory device comprising: a column address buffer including burst counters and generating first and second series of address signals in synchronization with every two clock cycles of a clock signal; a first column decoder, connected to said column address buffer, for decoding said first series of address signals in synchronization with every two clock cycles of said clock signal; a second column decoder, connected to said column address buffer, for decoding said second series of address signals in synchronization with every two clock cycles of said clock signal; a first sense amplifier, connected to said first column decoder, for amplifying a first data signal in accordance with a first column switch signal of said first column decoder and generating a voltage at a first read bus; a second sense amplifier, connected to said second column decoder, for amplifying a second data signal in accordance with a second column switch signal of said second column decoder and generating a voltage at a second read bus; a first first-stage data amplifier, connected to said first read bus, for amplifying the voltage of said first read bus and transmitting an amplified voltage of said first read bus to a read/write bus in synchronization with every two clock cycles of said clock signal; a second first-stage data amplifier, connected to said second read bus, for amplifying the voltage of said second read bus and transmitting an amplified voltage of said second read bus to said read/write bus in synchronization with every two clock cycles of said clock signal, said second first-stage data amplifier being operated time-divisionally with said first first-stage data amplifier; a second-stage data amplifier, connected to said read/write bus, for amplifying a voltage of said read/write bus in synchronization with every one clock cycle of said clock signal; and a data latch circuit, connected to said second-stage data amplifier, for latching an output of said second-stage data amplifier in synchronization with every one clock cycle of said clock signal to generate an output data signal.
Claim 3
Dependent Claim
75 words
The device as set forth in claim 1, wherein said first first-stage data amplifier is operated in accordance with a control signal obtained by delaying a control signal for said first column decoder, said second first-stage data amplifier being operated in accordance with a control signal obtained by delaying a control signal for said second column decoder. said second-stage data amplifier being operated on accordance with a control signal in synchronization with said clock signal.
Claim 4
Dependent Claim
122 words
A synchronous dynamic semiconductor memory device, comprising: a column address buffer having burst counters function and a plurality of outputs; a plurality of data paths, each connected to one of the outputs of said column address buffer, each of said data paths including a series of a column decoder, a sense amplifier and a first-stage data amplifier; a read/write bus connected to said data paths; a second-stage data amplifier connected to said read/write bus; and a data latch circuit connected to said second-stage amplifier, said data paths being operated in synchronization with every two clock cycles of a clock signal, said second-stage data amplifier and said data latch circuit being operated in synchronization with every one clock cycle of said clock signal.
Claim 5
Dependent Claim
122 words
A synchronous dynamic semiconductor memory device, comprising: a column address buffer having burst counters function and a plurality of outputs; a plurality of data paths, each connected to one of the outputs of said column address buffer, each of said data paths including a series of a column decoder, a sense amplifier and a first-stage data amplifier; a read/write bus connected to said data paths; a second-stage data amplifier connected to said read/write bus; and a data latch circuit connected to said second-stage amplifier, said data paths being operated in synchronization with every two clock cycles of a clock signal, said second-stage data amplifier and said data latch circuit being operated in synchronization with every one clock cycle of said clock signal.
Claim 6
Dependent Claim
27 words
The device as set as set forth in claim 3, wherein said first-stage data amplifiers of each of said data paths are operated time-divisionally with each other.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-12-29 | 2001-06-30 | 2001-12-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-12-29 | 2005-06-30 | 2005-12-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-12-29 | 2009-06-30 | 2009-12-30 | $7700.00 | Window Closed / Lapsed |