Pipelined memory having synchronous and asynchronous operating modes

Claim 2

A pipelined integrated circuit memory, comprising: a plurality of memory cells, each memory cell of the plurality of memory cells coupled to a bit line pair and to a word line; a column decoding circuit, coupled to the plurality of memory cells, for providing a data signal corresponding to data stored in a selected memory cell during a read cycle of the memory; an output register, having an input terminal coupled to the column decoding circuit, and an output terminal, the output register for receiving the data signal from the column decoding circuit, the output register responsive to a first clock signal; and an output enable circuit, coupled to the output register, for delaying the data signal for three clock cycles of the first clock signal during operation of the pipelined integrated circuit in a three-stage pipelining mode, and for delaying the output data for two clock cycles of the first clock signal during operation of the pipelined integrated circuit memory in a two-stage pipelining mode.

Claim 3

The pipelined integrated circuit memory of claim 1, wherein the output enable circuit comprises a plurality of series connected registers for receiving a write control signal, a second clock signal, and a pipelining control signal, and for providing an output enable signal on a third clock cycle of the second clock signal after the plurality of series connected registers has received the write control signal while operating in the three-stage pipelining mode, and for providing the output enable signal on a second clock cycle of the second clock signal while operating in the two-stage pipelining mode.

Claim 4

The pipelined integrated circuit memory of claim 2, wherein the first clock signal has a frequency equal to about one half a frequency of the second clock signal.

Claim 5

The pipelined integrated circuit memory of claim 1, further comprising a switch having an input terminal for receiving the data signal from the column decoding circuit, a control terminal for receiving the output enable signal, and an output terminal coupled to the input terminal of the output register.

Claim 6

The pipelined integrated circuit memory of claim 1, further comprising an amplifier circuit having an input terminal coupled to the output terminal of the output register, a control terminal for receiving the first clock signal, and an output terminal for providing an output data signal corresponding to the data signal.

Claim 7

The pipelined integrated circuit memory of claim 5, wherein the output data signal is characterized as being an ECL (emitter-coupled logic) level signal.

Claim 8

The pipelined integrated circuit memory claim 1, further comprising an asynchronous operating mode, wherein the output register provides the data signal on a next clock cycle of the first clock signal after an asynchronous mode control signal is asserted.

Claim 9

The pipelined integrated circuit memory of claim 1, wherein the plurality of memory cells are static random access memory cells.

Claim 10

A pipelined memory having synchronous and asynchronous operating modes, comprising: a plurality of memory cells, each memory cell of the plurality of memory cells coupled to a bit line pair and to a word line; a column decoding circuit, coupled to the plurality of memory cells, for providing a data signal corresponding to data stored in a selected memory cell during a read cycle of the memory; an output register, having an input terminal coupled to the column decoding circuit, and an output terminal, the output register for receiving the data signal from the column decoding circuit, the output register responsive to a first clock signal; and a plurality of output enable registers, coupled to the output register, for delaying the data signal for three clock cycles of the first clock signal during operation of the pipelined integrated circuit in a three-stage pipelining mode, for delaying the output data for two clock cycles of the first clock signal during operation of the pipelined integrated circuit memory in a two-stage pipelining mode, and for delaying the output data for one clock cycle of the first clock signal during operation of the pipelined integrated circuit memory in the asynchronous operating mode.

Claim 11

A pipelined memory having synchronous and asynchronous operating modes, comprising: a plurality of memory cells, each memory cell of the plurality of memory cells coupled to a bit line pair and to a word line; a column decoding circuit, coupled to the plurality of memory cells, for providing a data signal corresponding to data stored in a selected memory cell during a read cycle of the memory; an output register, having an input terminal coupled to the column decoding circuit, and an output terminal, the output register for receiving the data signal from the column decoding circuit, the output register responsive to a first clock signal; and a plurality of output enable registers, coupled to the output register, for delaying the data signal for three clock cycles of the first clock signal during operation of the pipelined integrated circuit in a three-stage pipelining mode, for delaying the output data for two clock cycles of the first clock signal during operation of the pipelined integrated circuit memory in a two-stage pipelining mode, and for delaying the output data for one clock cycle of the first clock signal during operation of the pipelined integrated circuit memory in the asynchronous operating mode.

Claim 12

The pipelined memory of claim 9, wherein the plurality of memory cells are static random access memory cells.

Claim 13

The pipelined memory of claim 9, wherein the plurality of output enable registers comprises a plurality of series connected registers for receiving a write control signal, a second clock signal, and a pipelining control signal, and for providing an output enable signal on a third clock cycle of the second clock signal after the plurality of series connected registers has received the write control signal while operating in the three-stage pipelining mode, for providing the output enable signal on a second clock cycle of the second clock signal while operating in the two-stage pipelining mode, and for providing the output enable signal of a first clock cycle of the second clock signal while operating in the asynchronous operating mode.

Claim 14

The pipelined memory of claim 11, wherein the first clock signal has a frequency equal to about one half a frequency of the second clock signal.

Claim 15

The pipelined memory of claim 9, further comprising an amplifier circuit having an input terminal coupled to the output terminal of the output register, a control terminal for receiving the first clock signal, and an output terminal for providing an output data signal corresponding to the data signal.

Claim 16

The pipelined memory of claim 13, wherein the output data signal is characterized as being an ECL (emitter-coupled logic) level signal.

Claim 17

A pipelined static random access memory having synchronous and asynchronous operating modes, comprising: a plurality of memory cells, each memory cell of the plurality of memory cells coupled to a bit line pair and to a word line; a column decoding circuit, coupled to the plurality of memory cells, for providing a data signal corresponding to data stored in a selected memory cell during a read cycle of the memory; an output register, having an input terminal coupled to the column decoding circuit, and an output terminal, the output register for receiving the data signal from the column decoding circuit, the output register responsive to a first clock signal; a plurality of series connected output enable registers, coupled to the output register, for delaying the data signal for three clock cycles of the first clock signal during operation of the pipelined integrated circuit in a three-stage pipelining mode, for delaying the output data for two clock cycles of the first clock signal during operation of the pipelined integrated circuit memory in a two-stage pipelining mode, and for delaying the output data for one clock cycle of the first clock signal during operation of the pipelined integrated circuit memory in the asynchronous operating mode; and a switch having an input terminal for receiving the data signal from the column decoding circuit, a control terminal for receiving the output enable signal, and an output terminal coupled to the input terminal of the output register.

Claim 18

A pipelined static random access memory having synchronous and asynchronous operating modes, comprising: a plurality of memory cells, each memory cell of the plurality of memory cells coupled to a bit line pair and to a word line; a column decoding circuit, coupled to the plurality of memory cells, for providing a data signal corresponding to data stored in a selected memory cell during a read cycle of the memory; an output register, having an input terminal coupled to the column decoding circuit, and an output terminal, the output register for receiving the data signal from the column decoding circuit, the output register responsive to a first clock signal; a plurality of series connected output enable registers, coupled to the output register, for delaying the data signal for three clock cycles of the first clock signal during operation of the pipelined integrated circuit in a three-stage pipelining mode, for delaying the output data for two clock cycles of the first clock signal during operation of the pipelined integrated circuit memory in a two-stage pipelining mode, and for delaying the output data for one clock cycle of the first clock signal during operation of the pipelined integrated circuit memory in the asynchronous operating mode; and a switch having an input terminal for receiving the data signal from the column decoding circuit, a control terminal for receiving the output enable signal, and an output terminal coupled to the input terminal of the output register.

Claim 19

The pipelined static random access memory of claim 15, wherein the plurality of series connected output enable registers are for receiving a write control signal, a second clock signal, and a pipelining control signal, and for providing an output enable signal on a third clock cycle of the second clock signal after the plurality of series connected registers has received the write control signal while operating in the three-stage pipelining mode, for providing the output enable signal on a second clock cycle of the second clock signal while operating in the two-stage pipelining mode, and for providing the output enable signal of a first clock cycle of the second clock signal while operating in the asynchronous operating mode.

Claim 20

The pipelined static random access memory of claim 16, wherein the plurality of series connected output enable registers comprises: a first register having an input terminal for receiving the write control signal, a control terminal for receiving the second clock signal, and an output terminal; a second register having an input terminal coupled to the output terminal of the first register, a control terminal for receiving the second clock signal, and an output terminal; a third register having an input terminal coupled to the output terminal of the second register, a first control terminal for receiving the second clock signal, a second control terminal for receiving mode control signal, and an output terminal; a fourth register having an input terminal coupled to the output terminal of the third register, a first control terminal for receiving the second clock signal, a second control terminal for receiving the control signal, and an output terminal; a fifth register having an input terminal coupled to the output terminal of the fourth register, a first control terminal for receiving the second clock signal, a second control terminal for receiving the asynchronous mode control signal, and an output terminal; and a sixth register having an input terminal coupled to the output terminal of the fifth register, a first control terminal for receiving the second clock signal, a second control terminal for receiving the asynchronous mode control signal, and an output terminal for providing the output enable signal.

Claim 21

The pipelined static random access memory of claim 17 wherein the first clock signal has a frequency equal to about one half a frequency of the second clock signal.

Claim 22

The pipelined memory of claim 18, further comprising an amplifier circuit having an input terminal coupled to the output terminal of the output register, a control terminal for receiving the first clock signal, and an output terminal for providing an output data signal corresponding to the data signal.

Claim 23

The pipelined memory of claim 19, wherein the output data signal is characterized as being an ECL (emitter-coupled logic) level signal.