US5155703A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Bicmos bit line load for a memory with improved reliability
Assignee: Motorola Solutions Inc
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Filing: 1990-07-06
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Granted: 1992-10-13
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Expires: 2010-07-06
Abstract
Abstract A BiCMOS (Bipolar Complementary Metal Oxide Semiconductor) bit line load for a memory with improved speed write recovery and improved reliability. Comprises a first bipolar transistor, a resistor, and a second and third bipolar transistors respectively coupled to first and second bit lines of a differential bit line pair. The improvement in speed is accomplished through the use of the bipolar transistors which generally switch faster than corresponding MOS transistors. The first bipolar transistor has a collector coupled to a power supply voltage terminal, a base for receiving a bias signal, and an emitter coupled to the collectors of the second and third bipolar transistors. The resistor is coupled between the collector and emitter of the first bipolar transistor. The bit line load has improved reliability by preventing self-boosting at the bases of the second and third bipolar transistors by decreasing their collector voltages enough during switching to bias them into saturation.
Inventors
- 👤 Scott G. Nogle
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 11:50
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/12; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/413; G11C11/417; G11C11/419
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
301 words
A bit line load coupled to a differential bit line pair in a block of a memory, the memory for performing read cycles and write cycles, comprising: bias means for providing an equalization signal at a logic low voltage when the memory block is selected during the write cycle, and for providing said equalization signal at a logic high voltage otherwise; a first transistor having a collector for receiving a first reference voltage, a base for receiving said equalization signal, and an emitter coupled to a bit line; a second transistor having a collector for receiving said first reference voltage, a base for receiving said equalization signal, and an emitter coupled to a complementary bit line; a third transistor having a first current electrode for receiving a second reference voltage, a control electrode coupled to a negative power supply voltage terminal, and a second current electrode coupled to said bit line; and a fourth transistor having a first current electrode for receiving said second reference voltage, a control electrode coupled to said negative power supply voltage terminal, and a second current electrode coupled to said complementary bit line; a fifth transistor having a collector coupled to a positive power supply voltage terminal, a base for receiving a first bias signal, and an emitter for providing said first reference voltage; and a resistor having a first terminal coupled to said positive power supply voltage terminal, and a second terminal coupled to said emitter of said fifth transistor; wherein a difference between said logic high voltage of said equalization signal minus one base-to-emitter diode voltage drop of either said first transistor or said second transistor, and said logic low voltage of said equalization signal, is limited to a predetermined voltage, said predetermined voltage assuring a given mean transistor life under worst case conditions.
Claim 2
Dependent Claim
301 words
A bit line load coupled to a differential bit line pair in a block of a memory, the memory for performing read cycles and write cycles, comprising: bias means for providing an equalization signal at a logic low voltage when the memory block is selected during the write cycle, and for providing said equalization signal at a logic high voltage otherwise; a first transistor having a collector for receiving a first reference voltage, a base for receiving said equalization signal, and an emitter coupled to a bit line; a second transistor having a collector for receiving said first reference voltage, a base for receiving said equalization signal, and an emitter coupled to a complementary bit line; a third transistor having a first current electrode for receiving a second reference voltage, a control electrode coupled to a negative power supply voltage terminal, and a second current electrode coupled to said bit line; and a fourth transistor having a first current electrode for receiving said second reference voltage, a control electrode coupled to said negative power supply voltage terminal, and a second current electrode coupled to said complementary bit line; a fifth transistor having a collector coupled to a positive power supply voltage terminal, a base for receiving a first bias signal, and an emitter for providing said first reference voltage; and a resistor having a first terminal coupled to said positive power supply voltage terminal, and a second terminal coupled to said emitter of said fifth transistor; wherein a difference between said logic high voltage of said equalization signal minus one base-to-emitter diode voltage drop of either said first transistor or said second transistor, and said logic low voltage of said equalization signal, is limited to a predetermined voltage, said predetermined voltage assuring a given mean transistor life under worst case conditions.
Claim 3
Dependent Claim
46 words
The bit line load of claim 1 wherein said second reference voltage is provided by a sixth transistor having a collector coupled to said positive power supply voltage terminal, a base for receiving said first bias signal, and an emitter for providing said second reference voltage.
Claim 4
Dependent Claim
23 words
The bit load of claim 2 wherein said first bias signal is substantially equal to a logic high voltage of said equalization signal.
Claim 5
Dependent Claim
20 words
The bit line load of claim 3 wherein said second reference voltage is substantially equal to said first reference voltage.
Claim 6
Dependent Claim
127 words
A bit line load coupled to a differential bit line pair in a block of a memory comprising: a first transistor having a collector coupled to a power supply voltage terminal, base for receiving a bias signal, and an emitter for providing a first reference voltage; a resistor having a first terminal coupled to said power supply voltage terminal, and a second terminal coupled to said emitter of said first transistor; a second transistor having a collector for receiving said first reference voltage, a base for receiving an equalization signal, and an emitter coupled to a bit line; and a thrid transistor having a collector for receiving said first reference voltage, a base for receiving said equalization signal, and an emitter coupled to a complementary bit line.
Claim 7
Dependent Claim
127 words
A bit line load coupled to a differential bit line pair in a block of a memory comprising: a first transistor having a collector coupled to a power supply voltage terminal, base for receiving a bias signal, and an emitter for providing a first reference voltage; a resistor having a first terminal coupled to said power supply voltage terminal, and a second terminal coupled to said emitter of said first transistor; a second transistor having a collector for receiving said first reference voltage, a base for receiving an equalization signal, and an emitter coupled to a bit line; and a thrid transistor having a collector for receiving said first reference voltage, a base for receiving said equalization signal, and an emitter coupled to a complementary bit line.
Claim 8
Dependent Claim
81 words
The bit line load of claim 5 further comprising: a fourth transistor having a first current electrode couple to said bit line, a control electrode coupled to a second power supply voltage terminal, and a second current electrode for receiving a second reference voltage; and a fifth transistor having a first current electrode coupled to said complementary bit line, a control electrode coupled to said second power supply voltage terminal, and a second current electrode for receiving said second reference voltage.
Claim 9
Dependent Claim
42 words
The bit line load of claim 6 further comprising: a sixth transistor having a first current eletrode coupled to said bit line, a control electrode for receiving a second equalization signal, and a second current electrode coupled to said complementary bit line.
Claim 10
Dependent Claim
44 words
The bit line load of claim 6 wherein said second reference voltage is provided by a seventh transistor having a collector coupled to said power supply voltage terminal, a base for receiving said bias signal, and an emitter for providing said second reference voltage.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-10-13 | 1996-04-13 | 1996-10-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-10-13 | 2000-04-13 | 2000-10-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-10-13 | 2004-04-13 | 2004-10-13 | $7700.00 | Window Closed / Lapsed |