US5923569A
Expired / Lapsed
US
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Method for designing layout of semiconductor integrated circuit semiconductor integrated circuit obtained by the same method and method for verifying timing thereof
Assignee: Panasonic Holdings Corp
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Filing: 1996-10-15
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Granted: 1999-07-13
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Expires: 2016-10-15
Abstract
Abstract First of all, a given logic circuit is divided into a combinational circuit portion and a register portion. The combinational circuit portion obtained by division is divided into a plurality of partial circuits having high connectivity. Each partial circuit is converted into a circuit having the transistor level. Then, a layout cell of the partial circuit having the transistor level is generated. Thereafter, arrangement and wiring are performed by using, as unit cells, a layout cell which corresponds to each register included in the register portion and the layout cell for each partial circuit in the combinational circuit so that a block layout is created. Accordingly, a layout having excellent characteristics can be created by a few kinds of cells in both circuits having the CMOS logic and the pass-transistor logic. In particular, the partial circuits having high connectivity are arranged in a cell in the circuit using the pass-transistor logic. Consequently, the optimum driving capability can be obtained and the layout having stable characteristics can be created. In addition, it is possible to ensure the superiority such as a reduction in area, the low consumed power, high-speed operation and the like.
Inventors
- 👤 Shinichi Kumashiro
- 👤 Hiroshi Mizuno
- 👤 Yasuhiro Tanaka
- 👤 Toshiyuki Moriwaki
- 👤 Youichirou Mae
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 03:15
CPC Classifications
G; G06; G06F; G06F30/00; G06F30/30; G06F30/32; G06F30/33; G06F30/3308; G06F30/39; H; H10; H10D; H10D84/00; H10D84/90; H10D84/903; H10D84/907; G06F2119/00; G06F2119/12
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
285 words
A method for designing the layout of a semiconductor integrated circuit, comprising: a circuit dividing processing of dividing a given logic circuit into a combinational circuit portion and a register portion; a transistor circuit converting processing of grasping a partial circuit in which signal paths are connected to each other, except for signal paths connected to the output of the register portion, in the combinational circuit portion, and converting the partial circuit into a circuit having the transistor level; a partial circuit layout generating processing of generating a layout cell of each partial circuit having the transistor level which is obtained by conversion; a block layout arranging and wiring processing of performing the arrangement and wiring of a cell-based layout by using, as unit cells, the layout cell generated for each partial circuit of the combinational circuit portion and each register included in the register portion respectively, and creating the block layout of the given logic circuit; wherein said partial circuit layout generating processing prepares the layouts of a plurality of subcells as a subcell library, the subcells being formed by at least one transistor in advance; a main cell generating processing of arranging and wiring some subcells of the plurality of subcells in the subcell library to be adjacent to each other to create a layout of a new cell, and registering the layout of the new cell as a main cell in a main cell library; and a partial circuit layout arranging and wiring processing of arranging and wiring a cell-based layout by using the subcell library and the main cell library as cell libraries, and generating a layout cell for each partial circuit having the transistor level which is obtained by conversion.
Claim 2
Independent Claim
285 words
A method for designing the layout of a semiconductor integrated circuit, comprising: a circuit dividing processing of dividing a given logic circuit into a combinational circuit portion and a register portion; a transistor circuit converting processing of grasping a partial circuit in which signal paths are connected to each other, except for signal paths connected to the output of the register portion, in the combinational circuit portion, and converting the partial circuit into a circuit having the transistor level; a partial circuit layout generating processing of generating a layout cell of each partial circuit having the transistor level which is obtained by conversion; a block layout arranging and wiring processing of performing the arrangement and wiring of a cell-based layout by using, as unit cells, the layout cell generated for each partial circuit of the combinational circuit portion and each register included in the register portion respectively, and creating the block layout of the given logic circuit; wherein said partial circuit layout generating processing prepares the layouts of a plurality of subcells as a subcell library, the subcells being formed by at least one transistor in advance; a main cell generating processing of arranging and wiring some subcells of the plurality of subcells in the subcell library to be adjacent to each other to create a layout of a new cell, and registering the layout of the new cell as a main cell in a main cell library; and a partial circuit layout arranging and wiring processing of arranging and wiring a cell-based layout by using the subcell library and the main cell library as cell libraries, and generating a layout cell for each partial circuit having the transistor level which is obtained by conversion.
Claim 3
Dependent Claim
39 words
The method for designing the layout of a semiconductor integrated circuit of claim 1, wherein the subcell library includes a plurality of subcells formed by two transistors having the same polarity whose source terminals are connected to each other.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-07-12 | 2003-01-11 | 2003-07-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-07-12 | 2007-01-11 | 2007-07-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-07-12 | 2011-01-11 | 2011-07-13 | $7700.00 | Window Closed / Lapsed |