US5493506A
Expired / Lapsed
US
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Integrated circuit device and method of designing same
Assignee: Renesas Electronics Corp
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Filing: 1993-09-14
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Granted: 1996-02-20
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Expires: 2013-09-14
Abstract
Abstract A register circuit an arithmetic circuit a register circuit and a logic circuit form a bit slice cell corresponding to a path of propagation connecting the circuits in this order. Similarly, an arithmetic circuit register circuits and a logic circuit form a bit slice cell and an arithmetic circuit register circuits and a logic circuit form a bit slice cell. The bit slice cells are arranged generally in parallel to form a bit slice circuit which prevents redundant lines for connecting the functional circuits, whereby the bit slice circuit is developed in a short period without a decreased degree of integration and prolonged delay time.
Inventors
- 👤 Kazuhiro Sakashita
- 👤 Isao Takimoto
- 👤 Terukazu Yusa
- 👤 Takeshi Hashizume
- 👤 Tatsunori Komoike
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 08:57
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/90; G; G06; G06F; G06F30/00; G06F30/30; G06F30/39
Claims Analysis
Total Claims: 39
Claim 1
Independent Claim
100 words
An integrated circuit device comprising: a plurality of bit slice cells, each of said bit cells including at least one functional circuit for achieving a predetermined function, said at least one functional circuit in each of said bit slice cells being arranged in at least one row and interconnected, said integrated circuit device being divided into a first region in which said bit slice cells are placed and a second region surrounding said first region, and said integrated circuit device further comprising a drive line surrounding said first region in said second region and used for driving said functional circuits.
Claim 2
Dependent Claim
100 words
An integrated circuit device comprising: a plurality of bit slice cells, each of said bit cells including at least one functional circuit for achieving a predetermined function, said at least one functional circuit in each of said bit slice cells being arranged in at least one row and interconnected, said integrated circuit device being divided into a first region in which said bit slice cells are placed and a second region surrounding said first region, and said integrated circuit device further comprising a drive line surrounding said first region in said second region and used for driving said functional circuits.
Claim 3
Dependent Claim
30 words
The integrated circuit device of claim 1, wherein said at least one functional circuit is arranged in a plurality of rows in at least one of said bit slice cells.
Claim 4
Dependent Claim
24 words
The integrated circuit device of claim 1, wherein said drive line is a power supply line for supplying power source to said functional circuits.
Claim 5
Dependent Claim
54 words
The integrated circuit device of claim 3, further comprising: a first power source trunk line provided in said first region and connected to said power supply line at a connecting point; and a second power source trunk line provided in said second region and connected to said power supply line at said connecting point.
Claim 6
Dependent Claim
62 words
The integrated circuit device of claim 3, further comprising: a first power source trunk line provided in said first region and connected to said power supply line at a first connecting point; and a second power source trunk line provided in said second region and connected to said power supply line at a second connecting point different from said first connecting point.
Claim 7
Dependent Claim
24 words
The integrated circuit device of claim 1, wherein said drive line is a clock line for supplying a clock signal to said functional circuits.
Claim 8
Dependent Claim
50 words
The integrated circuit device of claim 6, further comprising: a first clock trunk line provided in said first region and connected to said clock line at a connecting point; and a second clock trunk line provided in said second region and connected to said clock line at said connecting point.
Claim 9
Dependent Claim
58 words
The integrated circuit device of claim 6, further comprising: a first clock trunk line provided in said first region and connected to said clock line at a first connecting point; and a second clock trunk line provided in said second region and connected to said clock line at a second connecting point different from said first connecting point.
Claim 10
Dependent Claim
26 words
The integrated circuit device of claim 1, wherein said at least one functional circuit is arranged in a row in each of said bit slice cells.
Claim 11
Dependent Claim
33 words
The integrated circuit device of claim 9, wherein at least one of said functional circuits is an arithmetic circuit for performing an arithmetic operation in at least one of said bit slice cells.
Claim 12
Dependent Claim
31 words
The integrated circuit device of claim 10, wherein at least one of said functional circuits is a register circuit for holding data in at least one of said bit slice cells.
Claim 13
Dependent Claim
35 words
The integrated circuit device of claim 11, wherein at least one of said functional circuits is a logic circuit for performing a logic processing on data in at least one of said bit slice cells.
Claim 14
Dependent Claim
33 words
The integrated circuit device of claim 9, wherein said functional circuits which achieve the same function form a functional block, and said functional circuits are arranged in a column for each functional block.
Claim 15
Dependent Claim
59 words
The integrated circuit device of claim 13, said integrated circuit device being divided into a first region in which said bit slice cells are placed and a second region different from said first region, said integrated circuit device further comprising: a connecting line; and a memory circuit connected to said functional circuits with said connecting connecting line is minimized.
Claim 16
Dependent Claim
14 words
The integrated circuit device of claim 14, wherein said memory circuit includes a ROM.
Claim 17
Dependent Claim
84 words
The integrated circuit device of claim 15, wherein said ROM has at least a first connecting terminal connected to said connecting line, said integrated circuit device further comprising: at least a second connecting terminal corresponding to said at least first connecting terminal provided on the boundary between said first and second regions for connecting said connecting line and said functional circuits to each other, each of said at least a first and a second connecting terminals being aligned in first and second, rows, respectively.
Claim 18
Dependent Claim
21 words
The integrated circuit device of claim 16, wherein said first and second terminals are aligned in opposed relation to each other.
Claim 19
Dependent Claim
14 words
The integrated circuit device of claim 14, wherein said memory circuit includes a PLA.
Claim 20
Dependent Claim
73 words
The integrated circuit device of claim 18, wherein said PLA has a first connecting terminal connected to said connecting line, said integrated circuit device further comprising: a second connecting terminal corresponding to said first connecting terminal provided on the boundary between said first and second regions for connecting said connecting line and said functional circuits to each other, said first and second connecting terminals being aligned in first and second, opposed rows, respectively.
Claim 21
Dependent Claim
18 words
The integrated circuit device of claim 19, wherein said first and second terminals are opposed to each other.
Claim 22
Dependent Claim
41 words
The integrated circuit device of claim 14, wherein said second region surrounds said first region, said integrated circuit device further comprising a power supply line surrounding said first region in said second region for supplying power source to said memory circuit.
Claim 23
Dependent Claim
14 words
The integrated circuit device of claim 21, wherein said memory circuit includes a ROM.
Claim 24
Dependent Claim
14 words
The integrated circuit device of claim 21, wherein said memory circuit includes a PLA.
Claim 25
Dependent Claim
54 words
The integrated circuit device of claim 21, further comprising: a first power source trunk line provided in said first region and connected to said power supply line at a connecting point; and a second power source trunk line provided in said second region and connected to said power supply line at said connecting point.
Claim 26
Dependent Claim
62 words
The integrated circuit device of claim 21, further comprising: a first power source trunk line provided in said first region and connected to said power supply line at a first connecting point; and a second power source trunk line provided in said second region and connected to said power supply line at a second connecting point different from said first connecting point.
Claim 27
Dependent Claim
46 words
The integrated circuit device of claim 1, further comprising a clock driver for driving said functional circuits, said integrated circuit device being divided into a first region in which said bit slice cells are placed and a second region in which said clock driver is placed.
Claim 28
Dependent Claim
37 words
The integrated circuit device of claim 26, wherein said functional circuit is arranged in a row in each of said bit slice cells, and said clock driver is provided in corresponding relation to said bit slice cells.
Claim 29
Dependent Claim
45 words
The integrated circuit device of claim 26, wherein said functional circuits which achieve the same function form a functional block, said functional circuits are arranged in a column for each functional block, and said clock driver is provided in corresponding relation to said functional blocks.
Claim 30
Independent Claim
162 words
A method of designing an integrated circuit device, comprising the steps of: (a) specifying a predetermined range; (b) placing a connecting terminal at an edge of said predetermined range; (c) placing a plurality of bit slice cells generally in parallel in said predetermined range, each of said bit cells including at least one functional circuit for achieving a predetermined function; (d) placing one of said functional circuits in a first one of said bit slice cells to determine routing of wiring in said first bit slice cell; (e) placing another one of said functional circuits in an N-th one of said bit slice cells (where N is an integer more than 1) in consideration for placement and routing information of said functional circuit of an M-th one of said bit slice cells (where M is a natural number less than N) to determine routing of wiring in said N-th bit slice cell; and (f) determining routing of wiring between said functional circuits.
Claim 31
Independent Claim
162 words
A method of designing an integrated circuit device, comprising the steps of: (a) specifying a predetermined range; (b) placing a connecting terminal at an edge of said predetermined range; (c) placing a plurality of bit slice cells generally in parallel in said predetermined range, each of said bit cells including at least one functional circuit for achieving a predetermined function; (d) placing one of said functional circuits in a first one of said bit slice cells to determine routing of wiring in said first bit slice cell; (e) placing another one of said functional circuits in an N-th one of said bit slice cells (where N is an integer more than 1) in consideration for placement and routing information of said functional circuit of an M-th one of said bit slice cells (where M is a natural number less than N) to determine routing of wiring in said N-th bit slice cell; and (f) determining routing of wiring between said functional circuits.
Claim 32
Independent Claim
165 words
A method of designing an integrated circuit device, comprising the steps of: (a) making a logic design for an integrated circuit performing a predetermined processing to determine a logic design circuit; (b) dividing said logic design circuit into units of said predetermined processing to determine a plurality of bit slice cells each having at least one functional circuit for achieving a predetermined function; (c) placing one of said functional circuits in a first one of said bit slice cells to determine routing of wiring in said first bit slice cell (d) placing another one of said functional circuits in an N-th one of said bit slice cells (where N is an integer more than 1) in consideration for placement and routing information of said functional circuit of an M-th one of said bit slice cells (where M is a natural number less than N) to determine routing of wiring in said N-th bit slice cell; and (e) determining routing of wiring between said functional circuits.
Claim 33
Independent Claim
165 words
A method of designing an integrated circuit device, comprising the steps of: (a) making a logic design for an integrated circuit performing a predetermined processing to determine a logic design circuit; (b) dividing said logic design circuit into units of said predetermined processing to determine a plurality of bit slice cells each having at least one functional circuit for achieving a predetermined function; (c) placing one of said functional circuits in a first one of said bit slice cells to determine routing of wiring in said first bit slice cell (d) placing another one of said functional circuits in an N-th one of said bit slice cells (where N is an integer more than 1) in consideration for placement and routing information of said functional circuit of an M-th one of said bit slice cells (where M is a natural number less than N) to determine routing of wiring in said N-th bit slice cell; and (e) determining routing of wiring between said functional circuits.
Claim 34
Dependent Claim
12 words
The method of claim 30, wherein said M is equal to 1.
Claim 35
Independent Claim
88 words
A method of designing an integrated circuit device, comprising the steps of: (a) making a logic design for an integrated circuit performing a predetermined processing to determine a logic design circuit; (b) dividing said logic design circuit into functional circuits each for achieving a predetermined function; (c) specifying a predetermined region; (d) dividing said predetermined region into units of said predetermined processing to determine bit regions; (e) placing said functional circuits across said plurality of said bit regions; and (f) determining routing of wiring between said functional circuits.
Claim 36
Independent Claim
88 words
A method of designing an integrated circuit device, comprising the steps of: (a) making a logic design for an integrated circuit performing a predetermined processing to determine a logic design circuit; (b) dividing said logic design circuit into functional circuits each for achieving a predetermined function; (c) specifying a predetermined region; (d) dividing said predetermined region into units of said predetermined processing to determine bit regions; (e) placing said functional circuits across said plurality of said bit regions; and (f) determining routing of wiring between said functional circuits.
Claim 37
Independent Claim
101 words
A method of designing an integrated circuit device, comprising the steps of: (a) making a logic design for an integrated circuit performing a predetermined processing to determine a logic design circuit; (b) dividing said logic design circuit to determine a plurality of functional circuit blocks each including at least one functional circuit for achieving the same function; (c) specifying a predetermined region; (d) dividing said predetermined region into units of said predetermined processing to determine bit regions; (e) placing said functional circuit blocks across at least two of said bit regions; and (f) determining routing of wiring between said functional circuits.
Claim 38
Independent Claim
101 words
A method of designing an integrated circuit device, comprising the steps of: (a) making a logic design for an integrated circuit performing a predetermined processing to determine a logic design circuit; (b) dividing said logic design circuit to determine a plurality of functional circuit blocks each including at least one functional circuit for achieving the same function; (c) specifying a predetermined region; (d) dividing said predetermined region into units of said predetermined processing to determine bit regions; (e) placing said functional circuit blocks across at least two of said bit regions; and (f) determining routing of wiring between said functional circuits.
Claim 39
Dependent Claim
49 words
The method of claim 33, wherein said step (b) includes the step of: (b-1) dividing said functional circuit blocks into units of said predetermined processing, and said step (c) includes the step of: (c-1) placing said functional circuits in said bit regions, respectively, in accordance with said processing units.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-02-19 | 1999-08-21 | 2000-02-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-02-19 | 2003-08-21 | 2004-02-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-02-19 | 2007-08-21 | 2008-02-20 | $7700.00 | Window Closed / Lapsed |