Patent US2193897A successfully refreshed from Google Patents.
Patent US5920764A successfully refreshed from Google Patents.
US5920764A
Expired / Lapsed
US
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Process for restoring rejected wafers in line for reuse as new
Assignee: International Business Machines Corp
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Filing: 1997-09-30
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Granted: 1999-07-06
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Expires: 2017-09-30
Abstract
Abstract A process applicable to the restoration of defective or rejected semiconductor wafers to a defect-free form uses etchants and a variation of the Smart-Cut® process. Because of the use of the variation on the Smart-Cut® process, diffusion regions are removed without significantly affecting the specifications of the semiconductor wafer. Therefore, a defective or rejected wafer can be restored to near original condition for use in semiconductor manufacturing.
Inventors
- 👤 David R. Hanson
- 👤 Hance H. Huston, III
- 👤 Kris V. Srikrishnan
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 21:34
CPC Classifications
H; H10; H10P; H10P95/00; H10P90/00; H10P90/12; H10P90/16; H10P90/19; H10P90/1904; H10P90/1906; H10P90/1914; H10P90/1916; H10P95/90; H10W; H10W10/00; H10W10/10; H10W10/181; Y; Y10; Y10S; Y10S438/00; Y10S438/928; Y10S438/959; Y10S438/977
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
105 words
A method of forming a substrate portion comprising the steps of: providing a wafer comprising a substrate, said substrate having at least one of a metal portion and an oxide portion and at least a diffusion region; removing the at least one of the metal portion and the oxide portion; implanting ions into said substrate to form a buried layer therein, said buried layer being deeper than said diffusion region; heating said wafer to a temperature; and separating said wafer along said buried layer to remove a top surface layer of said wafer, whereby underlying portions of said wafer remain to form said substrate portion.
Claim 2
Independent Claim
105 words
A method of forming a substrate portion comprising the steps of: providing a wafer comprising a substrate, said substrate having at least one of a metal portion and an oxide portion and at least a diffusion region; removing the at least one of the metal portion and the oxide portion; implanting ions into said substrate to form a buried layer therein, said buried layer being deeper than said diffusion region; heating said wafer to a temperature; and separating said wafer along said buried layer to remove a top surface layer of said wafer, whereby underlying portions of said wafer remain to form said substrate portion.
Claim 3
Dependent Claim
21 words
The method according to claim 1, further comprising the step of planarizing the wafer prior to the step of implanting ions.
Claim 4
Dependent Claim
16 words
The method according to claim 2, wherein the step of planarizing includes depositing a leveling layer.
Claim 5
Dependent Claim
12 words
The method according to claim 3, wherein said leveling layer comprises spin-on-glass.
Claim 6
Dependent Claim
20 words
The method according to claim 1, further comprising the step of polishing said substrate portion after the step of separating.
Claim 7
Dependent Claim
30 words
The method according to claim 1, wherein the step of removing the at least one of the metal portion and the oxide portion includes etching using at least one etchant.
Claim 8
Dependent Claim
27 words
The method according to claim 6, wherein said at least one etchant is selected from the group consisting of a buffered hydrofluoric solution and a phosphoric solution.
Claim 9
Dependent Claim
14 words
The method according to claim 1, wherein the step of separating includes ultrasonic agitation.
Claim 10
Dependent Claim
11 words
The method according to claim 1, wherein the substrate is silicon.
Claim 11
Dependent Claim
23 words
The method according to claim 9, wherein said ions comprise hydrogen ions such that said buried layer is comprised of hydrogen and silicon.
Claim 12
Dependent Claim
38 words
The method according to claim 10, wherein said hydrogen ions are implanted at a dose in the range between about 2×10 16 and 10 17 ions/cm 2 with an energy in the range between 150 and 200 KeV.
Claim 13
Dependent Claim
34 words
The method according to claim 1, wherein said step of heating includes annealing at a range between about 400 and 600° C., for a time in the range between about 30 and 120 minutes.
Claim 14
Dependent Claim
27 words
The method according to claim 1, wherein said buried layer is formed at a depth between 1 and 2 μm beneath the top surface of said wafer.
Claim 15
Independent Claim
133 words
A method of forming a semiconductor substrate portion upon which semiconductor structures can be subsequently formed, comprising the steps of: providing a wafer comprising a semiconductor substrate, said semiconductor substrate having at least one of a metal portion and an oxide portion and at least a diffusion region; removing the at least one of the metal portion and the oxide portion; planarizing the semiconductor wafer; implanting hydrogen ions into said semiconductor substrate to form a buried layer therein, said buried layer being deeper than said diffusion region; heating said wafer to a temperature; separating said wafer along said buried layer to remove a top surface layer of said wafer; and polishing said semiconductor substrate portion after the step of separating, whereby underlying portions of said wafer remain to form said semiconductor substrate portion.
Claim 16
Independent Claim
133 words
A method of forming a semiconductor substrate portion upon which semiconductor structures can be subsequently formed, comprising the steps of: providing a wafer comprising a semiconductor substrate, said semiconductor substrate having at least one of a metal portion and an oxide portion and at least a diffusion region; removing the at least one of the metal portion and the oxide portion; planarizing the semiconductor wafer; implanting hydrogen ions into said semiconductor substrate to form a buried layer therein, said buried layer being deeper than said diffusion region; heating said wafer to a temperature; separating said wafer along said buried layer to remove a top surface layer of said wafer; and polishing said semiconductor substrate portion after the step of separating, whereby underlying portions of said wafer remain to form said semiconductor substrate portion.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-07-05 | 2003-01-04 | 2003-07-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-07-05 | 2007-01-04 | 2007-07-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-07-05 | 2011-01-04 | 2011-07-06 | $7700.00 | Window Closed / Lapsed |