US5913048A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Dispatching instructions in a processor supporting out-of-order execution
Assignee: International Business Machines Corp
•
Filing: 1997-03-31
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Granted: 1999-06-15
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Expires: 2017-03-31
Abstract
Abstract The invention relates to a method for issuing instructions in a processor. In one version of the invention, the method includes the steps of assigning an identification tag to an instruction, and dispatching the instruction, the identification tag and source information to an execution queue.
Inventors
- 👤 Hoichi Cheong
- 👤 Hung Qui Le
- 👤 John Stephen Muhich
- 👤 Steven Wayne White
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 03:31
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3854; G06F9/3856; G06F9/3836; G06F9/3838; G06F9/384; G06F9/3842; G06F9/3858; G06F9/3861; G06F9/3863
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
82 words
A method for dispatching instructions in a processor, the method comprising the steps of: (a) assigning an identification tag to an instruction, the identification tag being unique to the instruction; (b) dispatching instruction information to a queue, the instruction information including the instruction, the identification tag assigned to the instruction, and source information relating to the instruction; and (c) updating at least one table with additional information related to the instruction, the additional information including the identification tag assigned to the instruction.
Claim 2
Independent Claim
82 words
A method for dispatching instructions in a processor, the method comprising the steps of: (a) assigning an identification tag to an instruction, the identification tag being unique to the instruction; (b) dispatching instruction information to a queue, the instruction information including the instruction, the identification tag assigned to the instruction, and source information relating to the instruction; and (c) updating at least one table with additional information related to the instruction, the additional information including the identification tag assigned to the instruction.
Claim 3
Dependent Claim
27 words
The method of claim 1 wherein the step of updating at least one table includes updating a table with future state information when the instruction is dispatched.
Claim 4
Dependent Claim
20 words
The method of claim 2 wherein the table comprises a plurality of entries which correspond to registers of the processor.
Claim 5
Dependent Claim
42 words
The method of claim 3 wherein the step of updating the future state information comprises writing the identification tag assigned to the instruction into a field of an entry in the table, said entry corresponding to a register targeted by the instruction.
Claim 6
Dependent Claim
32 words
The method of claim 1 wherein the step of updating at least one table includes the step of updating a stack buffer with restart information when the instruction comprises an interruptible instruction.
Claim 7
Dependent Claim
26 words
The method of claim 5 wherein updating the stack buffer with restart information comprises writing a logical address of the interruptible instruction into the stack buffer.
Claim 8
Dependent Claim
32 words
The method of claim 1 wherein the instruction targets a register and the step of updating at least one table includes the step of updating a history buffer with dispatch state information.
Claim 9
Dependent Claim
33 words
The method of claim 7 wherein updating the history buffer with dispatch state information comprises writing table information into the history buffer, the table information corresponding to the register targeted by the instruction.
Claim 10
Independent Claim
89 words
An apparatus for dispatching instructions in a processor, the apparatus comprising: (a) tag assignment means for assigning an identification tag to an instruction, the identification tag being unique to the instruction; (b) dispatching means for dispatching instruction information to a queue, the instruction information including the instruction, the identification tag assigned to the instruction, and source information relating to the instruction; and (c) updating means for updating at least one table with additional information related to the instruction, the additional information including the identification tag assigned to the instruction.
Claim 11
Independent Claim
89 words
An apparatus for dispatching instructions in a processor, the apparatus comprising: (a) tag assignment means for assigning an identification tag to an instruction, the identification tag being unique to the instruction; (b) dispatching means for dispatching instruction information to a queue, the instruction information including the instruction, the identification tag assigned to the instruction, and source information relating to the instruction; and (c) updating means for updating at least one table with additional information related to the instruction, the additional information including the identification tag assigned to the instruction.
Claim 12
Dependent Claim
21 words
The apparatus of claim 9 wherein the updating means updates a table with future state information when the instruction is dispatched.
Claim 13
Dependent Claim
22 words
The apparatus of claim 10 wherein the table comprises a plurality of entries, each entry corresponding to a register of the processor.
Claim 14
Dependent Claim
35 words
The apparatus of claim 11 wherein the updating means writes the identification tag of the instruction into a field of an entry in the table, said entry corresponding to a register targeted by the instruction.
Claim 15
Dependent Claim
23 words
The apparatus of claim 9 wherein the update means updates a stack buffer with restart information when the instruction is an interruptible instruction.
Claim 16
Dependent Claim
21 words
The apparatus of claim 13 wherein the update means writes the logical address of the interruptible instruction into the stack buffer.
Claim 17
Dependent Claim
29 words
The apparatus of claim 9 wherein the instruction targets a register and wherein the update means updates a history buffer with dispatch state information when the instruction is dispatched.
Claim 18
Dependent Claim
27 words
The apparatus of claim 15 wherein the update means writes table information into the history buffer, the table information corresponding to the register targeted by the instruction.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-06-14 | 2002-12-14 | 2003-06-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-06-14 | 2006-12-14 | 2007-06-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-06-14 | 2010-12-14 | 2011-06-15 | $7700.00 | Window Closed / Lapsed |