Patent US5099308A successfully refreshed from Google Patents.
US5509130A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method and apparatus for grouping multiple instructions, issuing grouped instructions simultaneously, and executing grouped instructions in a pipelined processor
Assignee: Sun Microsystems Inc
•
Filing: 1994-12-14
•
Granted: 1996-04-16
•
Expires: 2014-12-14
Abstract
Abstract In a pipelined processor, an instruction queue and an instruction control unit is provided to group and issue m instructions simultaneously per clock cycle for execution. An integer and a floating point function unit capable of generating n 1 and n 2 integer and floating point results per clock cycle respectively, where n 1 and n 2 are sufficiently large to support m instructions being issued per clock cycle, is also provided to complement the instruction queue and instruction control unit. The pipeline stages are divided into integer and floating point pipeline stages where the early floating point stages overlap with the later integer pipeline stages. The instruction queue stores sequential instructions of a program and target instructions of a branch instruction of the program, fetched from the instruction cache. The instruction control unit decodes the instructions, detects operands cascading from instruction to instruction, group instructions into instruction groups of at most m instructions applying a number of exclusion rules, and issuing the grouped instructions simultaneously to the integer and/or floating point unit for execution. The exclusion rules reflect the resource characteristics and the particular implementation of the pipelined processor. The instruction control unit also tracks the history of the instruction groups and uses the history in conjunction with the exclusion rules in forming the instruction groups.
Inventors
- 👤 Richard D. Trauben
- 👤 Sunil Nanda
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 18:45
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3802; G06F9/3804; G06F9/3836; G06F9/3838; G06F9/3853; G06F9/3854; G06F9/3856; G06F9/3867
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
105 words
In a pipelined processor comprising an instruction control unit, a method for queuing and requeuing instructions for said instruction control unit, said method comprising the steps of: a) queuing a plurality of sequential instructions in a sequential instruction queue; b) queuing a plurality of branch target instructions in a branch target instruction queue; c) providing selected ones of said sequential and branch target instructions from said sequential and target instruction queues to said instruction control unit; and d) requeuing said instructions provided to said instruction control unit into said sequential queue if said provided instructions are not issued for execution by said instruction control unit.
Claim 2
Dependent Claim
105 words
In a pipelined processor comprising an instruction control unit, a method for queuing and requeuing instructions for said instruction control unit, said method comprising the steps of: a) queuing a plurality of sequential instructions in a sequential instruction queue; b) queuing a plurality of branch target instructions in a branch target instruction queue; c) providing selected ones of said sequential and branch target instructions from said sequential and target instruction queues to said instruction control unit; and d) requeuing said instructions provided to said instruction control unit into said sequential queue if said provided instructions are not issued for execution by said instruction control unit.
Claim 3
Dependent Claim
32 words
The method as set forth in claim 1, wherein, said sequential and target instructions are queued into said sequential and target queues respectively at a rate of four instructions per clock cycle.
Claim 4
Dependent Claim
35 words
The method as set forth in claim 1, wherein, said instructions are provided to said instruction control unit from said sequential and branch target instruction queues at a rate of three instructions per clock cycle.
Claim 5
Dependent Claim
155 words
In a pipelined processor comprising an integer and a floating point function unit, a method grouping and issuing multiple instructions simultaneously to said integer and floating point units for execution, said method comprising the steps of: a) receiving m instructions from an instruction queue; b) decoding opcodes of said m instructions; c) detecting operands used in other instructions that cascade from one instruction to another; d) applying a plurality of exclusion rules to each of said m instructions to determine whether said instruction is to be excluded from issuance to said integer and floating point units for execution in conjunction with the other instructions; e) groundling said instructions that are not excluded and issuing them simultaneously to said integer and floating point units for execution; and f) tracking history of said issued instruction group, said history being used when detecting cascading operands in said step c) and applying said exclusion rules in said step d).
Claim 6
Dependent Claim
155 words
In a pipelined processor comprising an integer and a floating point function unit, a method grouping and issuing multiple instructions simultaneously to said integer and floating point units for execution, said method comprising the steps of: a) receiving m instructions from an instruction queue; b) decoding opcodes of said m instructions; c) detecting operands used in other instructions that cascade from one instruction to another; d) applying a plurality of exclusion rules to each of said m instructions to determine whether said instruction is to be excluded from issuance to said integer and floating point units for execution in conjunction with the other instructions; e) groundling said instructions that are not excluded and issuing them simultaneously to said integer and floating point units for execution; and f) tracking history of said issued instruction group, said history being used when detecting cascading operands in said step c) and applying said exclusion rules in said step d).
Claim 7
Dependent Claim
44 words
The method as set forth in claim 4, wherein, m equals three; said three instructions are received from said instruction queue at a rate of three instructions per clock cycle; said steps b), c), d), e) and f) are performed within one clock cycle.
Claim 8
Dependent Claim
71 words
The method as set forth in claim 4, wherein, said exclusion rules comprise a plurality of "Break After" and a plurality of "Break Before" exclusion rules, said "Break After" exclusion rules terminate instruction grouping after the instruction being considered based on relationships among preceding instructions, and said "Break Before" exclusion rules terminate instruction group before the instruction being considered based on the usage of hardware resources available to said pipelined processor.
Claim 9
Dependent Claim
124 words
In a pipelined processor comprising an instruction control unit, an apparatus for queuing and requeuing instructions for said instruction control unit comprising: a) first queuing means for queuing a plurality of sequential instructions; b) second queuing means for queuing a plurality of branch target instructions; c) first multiplexor means coupled to said first and second queuing means and said instruction control unit for providing selected ones of said sequential and branch target instructions to said instruction control unit; and d) second multiplexor means coupled to said first and second queuing means and said instruction control unit for requeuing said instructions provided to said instruction control unit into said sequential queue if said provided instructions are not issued for execution by said instruction control unit.
Claim 10
Dependent Claim
124 words
In a pipelined processor comprising an instruction control unit, an apparatus for queuing and requeuing instructions for said instruction control unit comprising: a) first queuing means for queuing a plurality of sequential instructions; b) second queuing means for queuing a plurality of branch target instructions; c) first multiplexor means coupled to said first and second queuing means and said instruction control unit for providing selected ones of said sequential and branch target instructions to said instruction control unit; and d) second multiplexor means coupled to said first and second queuing means and said instruction control unit for requeuing said instructions provided to said instruction control unit into said sequential queue if said provided instructions are not issued for execution by said instruction control unit.
Claim 11
Dependent Claim
31 words
The apparatus as set forth in claim 7, wherein, said first and second queuing means queue said sequential and target instructions respectively at a rate of four instructions per clock cycle.
Claim 12
Dependent Claim
30 words
The apparatus as set forth in claim 7, wherein, said first multiplexor means provides said instructions to said instruction control unit at a rate of three instructions per clock cycle.
Claim 13
Dependent Claim
190 words
In a pipelined processor comprising an integer and a floating point %unction unit, an apparatus for grouping and issuing multiple instructions simultaneously to said integer and floating point units for execution comprising: a) receiving means for receiving m instructions from an instruction queue; b) decoding means coupled to said receiving means for decoding opcodes of said m instructions; c) detecting means coupled to said receiving means for detecting operands used in other instructions that cascade from one instruction to another; d) grouping means coupled to said decoding and detecting means for applying a plurality of exclusion rules to each of said m instructions to determine whether said instruction is to be excluded from issuance to said integer and floating point units for execution in conjunction with the other instructions, grouping said instructions that are not excluded, and issuing them simultaneously to said integer and floating point units for execution; and e) tracking means coupled to said detecting and grouping means for tracking history of said issued instruction group, said history being used by said detecting means and said grouping means when detecting cascading operands and applying the exclusion rules respectively.
Claim 14
Dependent Claim
190 words
In a pipelined processor comprising an integer and a floating point %unction unit, an apparatus for grouping and issuing multiple instructions simultaneously to said integer and floating point units for execution comprising: a) receiving means for receiving m instructions from an instruction queue; b) decoding means coupled to said receiving means for decoding opcodes of said m instructions; c) detecting means coupled to said receiving means for detecting operands used in other instructions that cascade from one instruction to another; d) grouping means coupled to said decoding and detecting means for applying a plurality of exclusion rules to each of said m instructions to determine whether said instruction is to be excluded from issuance to said integer and floating point units for execution in conjunction with the other instructions, grouping said instructions that are not excluded, and issuing them simultaneously to said integer and floating point units for execution; and e) tracking means coupled to said detecting and grouping means for tracking history of said issued instruction group, said history being used by said detecting means and said grouping means when detecting cascading operands and applying the exclusion rules respectively.
Claim 15
Dependent Claim
46 words
The apparatus as set forth in claim 10, wherein, m equals three; said receiving means receives said three instructions from said instruction queue at a rate of three instructions per clock cycle; said decoding, detecting, grouping and tracking means perform their operations within one clock cycle.
Claim 16
Dependent Claim
71 words
The apparatus as set forth in claim 10, wherein, said exclusion rules comprise a plurality of "Break After" and a plurality of "Break Before" exclusion rules, said "Break After" exclusion rules terminate instruction grouping after the instruction being considered based on relationships among preceding instructions, and said "Break Before" exclusion rules terminate instruction grouping before the instruction being considered based on the usage of hardware resources available to said pipelined processor.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-04-16 | 1999-10-16 | 2000-04-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-04-16 | 2003-10-16 | 2004-04-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-04-16 | 2007-10-16 | 2008-04-16 | $7700.00 | Window Closed / Lapsed |