US5664120A — Method for executing instructions and execution u…

Claim 1

Independent Claim 206 words

A method for executing instructions within a processor, said processor having associated therewith a plurality of rename buffers which temporarily store results of instructions, a plurality of registers, and an execution unit, said execution unit having a reservation data structure, wherein said reservation data structure includes a plurality of entries which store instructions to be executed by said execution unit, and a single operand buffer, which stores one or more operands of a single instruction, wherein said processor completes instructions according to a program order, said method comprising: receiving an instruction at said execution unit; storing said instruction within said reservation data structure within said execution unit, said instruction being stored in association with information specifying a source of an operand of said instruction, wherein sources of operands of instructions include said plurality of rename buffers and said plurality of registers; determining if said instruction is a next instruction to be executed by said execution unit; in response to said determination, loading said operand of said instruction from said specified source into said single operand entry; and executing said instruction within said execution unit utilizing said operand within said single operand entry, wherein a portion of said reservation data structure allocated to operand storage is reduced.

Claim 2

Independent Claim 206 words

A method for executing instructions within a processor, said processor having associated therewith a plurality of rename buffers which temporarily store results of instructions, a plurality of registers, and an execution unit, said execution unit having a reservation data structure, wherein said reservation data structure includes a plurality of entries which store instructions to be executed by said execution unit, and a single operand buffer, which stores one or more operands of a single instruction, wherein said processor completes instructions according to a program order, said method comprising: receiving an instruction at said execution unit; storing said instruction within said reservation data structure within said execution unit, said instruction being stored in association with information specifying a source of an operand of said instruction, wherein sources of operands of instructions include said plurality of rename buffers and said plurality of registers; determining if said instruction is a next instruction to be executed by said execution unit; in response to said determination, loading said operand of said instruction from said specified source into said single operand entry; and executing said instruction within said execution unit utilizing said operand within said single operand entry, wherein a portion of said reservation data structure allocated to operand storage is reduced.

Claim 3

Dependent Claim 123 words

The method for executing instructions within a processor of claim 1, said method further comprising: in response to a determination that said instruction in not said next instruction to be executed by said execution unit, determining whether said information specifies that said source of said operand is said plurality of rename buffers and whether said operand is scheduled to be transferred from one of said plurality of rename buffers to one of said plurality of registers; and in response to a determination that said information specifies that said source of said operand is said plurality of rename buffers and that said operand is scheduled to be transferred, updating said information to indicate that said source of said operand is said plurality of registers.

Claim 4

Dependent Claim 72 words

The method for executing instructions within a processor of claim 2, said processor further comprising a completion unit which completes instructions executed by said processor according to said program order, wherein said step of determining whether said operand is scheduled to be transferred from one of said plurality of rename buffers to one of said plurality of registers comprises polling said completion unit to determine whether said instruction is scheduled for completion.

Claim 5

Dependent Claim 71 words

The method for executing instructions within a processor of claim 1, wherein said information also specifies a destination rename buffer among said plurality of rename buffers, said method further comprising: finishing said instruction by storing a result of said instruction within said destination rename buffer; and thereafter, completing said instruction according to said program order by transferring said result from said destination rename buffer to one of said plurality of registers.

Claim 6

Dependent Claim 44 words

The method for executing instructions within a processor of claim 1, wherein said information comprises a tag stored within said reservation data structure that specifies which one of said plurality of rename buffers or said plurality of registers is said source of said operand.

Claim 7

Dependent Claim 58 words

The method for executing instructions within a processor of claim 1, wherein said step of determining whether said instruction is a next instruction to be executed comprises determining whether each operand of said instruction is available and whether a resource within said execution unit is available to perform an operation upon said each operand indicated by said instruction.

Claim 8

Dependent Claim 232 words

A processor, comprising: a plurality of rename buffers for temporarily storing results of instructions; a plurality of registers, wherein said processor completes instructions according to a program order by transferring results of instructions from particular rename buffers among said plurality of rename buffers to particular registers among said plurality of registers; an execution unit, said execution unit having: a reservation data structure, wherein said reservation data structure includes a plurality of entries for storing instructions to be executed by said execution unit and a single operand buffer for storing one or more operands of a single instruction; means for receiving an instruction at said execution unit; means for storing said instruction within said reservation data structure, wherein said instruction is stored in association with information specifying a source of an operand of said instruction, wherein sources of operands of instructions include said plurality of rename buffers and said plurality of registers; means for determining if said instruction is a next instruction to be executed by said execution unit; means for loading said operand of said instruction from said specified source into said single operand entry in response to a determination that said instruction is a next instruction to be executed by said execution unit; and means for executing said instruction utilizing said operand within said single operand entry, wherein a portion of said reservation data structure allocated to operand storage is reduced.

Claim 9

Dependent Claim 232 words

A processor, comprising: a plurality of rename buffers for temporarily storing results of instructions; a plurality of registers, wherein said processor completes instructions according to a program order by transferring results of instructions from particular rename buffers among said plurality of rename buffers to particular registers among said plurality of registers; an execution unit, said execution unit having: a reservation data structure, wherein said reservation data structure includes a plurality of entries for storing instructions to be executed by said execution unit and a single operand buffer for storing one or more operands of a single instruction; means for receiving an instruction at said execution unit; means for storing said instruction within said reservation data structure, wherein said instruction is stored in association with information specifying a source of an operand of said instruction, wherein sources of operands of instructions include said plurality of rename buffers and said plurality of registers; means for determining if said instruction is a next instruction to be executed by said execution unit; means for loading said operand of said instruction from said specified source into said single operand entry in response to a determination that said instruction is a next instruction to be executed by said execution unit; and means for executing said instruction utilizing said operand within said single operand entry, wherein a portion of said reservation data structure allocated to operand storage is reduced.

Claim 10

Dependent Claim 118 words

The processor of claim 7, and further comprising: means, responsive to a determination that said instruction in not said next instruction to be executed by said execution unit, for determining whether said information specifies that said source of said operand is said plurality of rename buffers and whether said operand is scheduled to be transferred from one of said plurality of rename buffers to one of said plurality of registers; and means, responsive to a determination that said information specifies that said source of said operand is said plurality of rename buffers and that said operand is scheduled to be transferred, for updating said information to indicate that said source of said operand is said plurality of registers.

Claim 11

Dependent Claim 68 words

The processor of claim 8, said processor further comprising a completion unit which completes instructions executed by said processor according to said program order, wherein said means for determining whether said operand is scheduled to be transferred from one of said plurality of rename buffers to one of said plurality of registers comprises means for polling said completion unit to determine whether said instruction is scheduled for completion.

Claim 12

Dependent Claim 69 words

The processor of claim 8, wherein said information also specifies a destination rename buffer among said plurality of rename buffers, said processor further comprising: means for finishing said instruction by storing a result of said instruction within said destination rename buffer; and means for thereafter completing said instruction according to said program order by transferring said result from said destination rename buffer to one of said plurality of registers.

Claim 13

Dependent Claim 38 words

The processor of claim 8, wherein said information comprises a tag stored within said reservation data structure that specifies which one of said plurality of rename buffers or said plurality of registers is said source of said operand.

Claim 14

Dependent Claim 54 words

The processor of claim 8, wherein said means for determining whether said instruction is a next instruction to be executed comprises means for determining whether each operand of said instruction is available and whether a resource within said execution unit is available to perform an operation upon said each operand indicated by said instruction.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	2000-09-01	2001-03-03	2001-09-02	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	2004-09-01	2005-03-03	2005-09-02	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2008-09-01	2009-03-03	2009-09-02	$7700.00	Window Closed / Lapsed

Method for executing instructions and execution unit instruction reservation table within an in-order completion processor

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