Patent US5911052A successfully refreshed from Google Patents.
US5911052A
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Split transaction snooping bus protocol
Assignee: Oracle America Inc
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Filing: 1996-07-01
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Granted: 1999-06-08
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Expires: 2016-07-01
Abstract
Abstract A split transaction snooping bus protocol and architecture is provided for use in a system having one or many such buses. Circuit boards including CPU or other devices and/or distributed memory, data input/output buffers, queues including request tag queues, coherent input queues ("CIQ"), and address controller implementing address bus arbitration plug-into one or more split transaction snooping bus systems. All devices snoop on the address bus to learn whether an identified line is owned or shared, and an appropriate owned/shared signal is issued. Receipt of an ignore signal blocks CIQ loading of a transaction until the transaction is reloaded and ignore is deasserted. Ownership of a requested memory line transfers immediately at time of request. Asserted requests are queued such that state transactions on the address bus occur atomically logically without dependence upon the request. Subsequent requests for the same data are tagged to become the responsibility of the owner-requestor. A subsequent requestor's activities are not halted awaiting grant and completion of an earlier request transaction. Processor-level cache changes state upon receipt of transaction data. A single multiplexed arbitration bus carries address bus and data bus request transactions, which transactions are each two-cycles in length.
Inventors
- 👤 Ashok Singhal
- 👤 Bjorn Liencres
- 👤 Jeff Price
- 👤 Frederick M. Cerauskis
- 👤 David Broniarczyk
- 👤 Gerald Cheung
- 👤 Erik Hagersten
- 👤 Nalini Agarwal
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 10:36
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F13/36; G06F13/368; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0806; G06F12/0815; G06F12/0831
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
192 words
For use with a computer system having at least one memory unit and at least one device able to initiate and/or respond to a transaction, each said device being associated with an address controller, a protocol for a split transaction bus system having at least an address bus that is snooped upon by each said device, said split transaction bus system protocol including the following steps: providing an address bus, coupled to each said device, carrying address data associated with at least one transaction; providing a data bus separate from said address bus, coupled to each said device, carrying transaction data associated with at least one transaction; providing a multiplexed arbitration bus, coupled to each said device, carrying address bus and data bus transaction requests for at least some of said devices, wherein for each transaction, address data is placed on said address bus in a same clock cycle with placement of a transaction request on said arbitration bus; wherein each said device snoops on said address bus to learn whether an identified memory line is owned or shared whereupon an appropriate owned or shared signal is asserted on said bus system.
Claim 2
Dependent Claim
192 words
For use with a computer system having at least one memory unit and at least one device able to initiate and/or respond to a transaction, each said device being associated with an address controller, a protocol for a split transaction bus system having at least an address bus that is snooped upon by each said device, said split transaction bus system protocol including the following steps: providing an address bus, coupled to each said device, carrying address data associated with at least one transaction; providing a data bus separate from said address bus, coupled to each said device, carrying transaction data associated with at least one transaction; providing a multiplexed arbitration bus, coupled to each said device, carrying address bus and data bus transaction requests for at least some of said devices, wherein for each transaction, address data is placed on said address bus in a same clock cycle with placement of a transaction request on said arbitration bus; wherein each said device snoops on said address bus to learn whether an identified memory line is owned or shared whereupon an appropriate owned or shared signal is asserted on said bus system.
Claim 3
Dependent Claim
65 words
The split transaction bus system protocol of claim 1, further including transferring ownership of a said identified memory line to a said device on a packet on said address bus, regardless of whether data associated with an associated said transaction is as yet transferred, and wherein responding to a subsequent request for said memory line is a responsibility of a said device having said ownership.
Claim 4
Dependent Claim
45 words
The split transaction bus system protocol of claim 2, wherein an initiating said device pushes data and if a responding said device is presently unable to accept said data, a data cancel signal is asserted, whereupon said responding device assumes responsibility for pulling said data.
Claim 5
Dependent Claim
48 words
The split transaction bus system protocol of claim 3, wherein: a responding said device tracks write-type operations that it is to pull; an initiating said device responds with said data when said responding said device drives an appropriate dataID signal on said data bus, thereupon pulling said data.
Claim 6
Dependent Claim
53 words
The split transaction bus system protocol of claim 4, wherein if said initiating device asserts an owned signal for a writeback transaction, a data transfer occurs without writing said data to memory, and said initiating device relinquishes ownership of an appropriate said memory line when an address packet for said writeback transaction issues.
Claim 7
Dependent Claim
35 words
The split transaction bus system protocol of claim 5, wherein a device issuing a said writeback transaction cancels said writeback transaction if bus-level tags associated with said device indicate said device is not the owner.
Claim 8
Dependent Claim
21 words
The split transaction bus system protocol of claim 6, wherein said writeback transaction is cancelled by assertion of an OWNED-type signal.
Claim 9
Dependent Claim
21 words
The split transaction bus system protocol of claim 4, wherein if an ignore signal is asserted, no data packets are issued.
Claim 10
Dependent Claim
43 words
The split transaction bus system protocol of claim 1, wherein: said computer system includes a plurality of circuit cards that contain said device devices, each said circuit card including an address controller having a mechanism for arbitrating requests to access said address bus.
Claim 11
Dependent Claim
40 words
The split transaction bus system protocol of claim 9, wherein an owned or shared state is discerned by a snooping said device from transaction address data and from memory on a one of said circuit boards associated with said device.
Claim 12
Dependent Claim
41 words
The split transaction bus system protocol of claim 10, wherein asserted requests are queued such that state transactions on said address bus occur atomically, logically, without dependence upon a response thereto; said split transaction bus functioning without blocking a transaction request.
Claim 13
Dependent Claim
77 words
The split transaction bus system protocol of claim 9, further including: providing a data ID bus carrying dataID uniquely identifying data responsive to a transaction request; wherein said address data for each transaction includes a sourceID uniquely identifying which of said circuit cards contains a said device initiating said transaction, and uniquely identifying said transaction; and wherein said dataID and said sourceID permit matching packets on said data bus with earlier placed packets on said address bus.
Claim 14
Dependent Claim
98 words
The split transaction bus system protocol of claim 9, wherein each of said circuit boards includes a coherent in queue into which all coherent transactions requested for a said device associated with the circuit board are loaded, absent assertion by said computer system of an ignore signal, prior to assertion; wherein upon deassertion of said ignore signal, a said transaction is then reissued and, absent assertion of an ignore signal relevant to the reissued said transaction, said reissued transaction is loaded into said coherent in queue and appears on said split transaction bus system as a valid transaction.
Claim 15
Dependent Claim
19 words
The split transaction bus system protocol of claim 13, wherein said ignore signal is time-multiplexed onto said address bus.
Claim 16
Dependent Claim
93 words
The split transaction bus system protocol of claim 13, wherein: said computer system includes cache lines and a bus-level tag memory storing state information for each of said cache lines, said bus-level tag memory being used by said devices for snooping; and each of said circuit cards includes a device-level tag memory storing state information for each of said cache lines associated with one of said devices; further including comparing state information in said bus-level tag memory and in said device-level tag memory to identify a request that is a candidate for reordering.
Claim 17
Dependent Claim
73 words
The split transaction bus system protocol of claim 15, wherein: a transaction is loaded into a said coherent in queue if there is an identity of state in said bus-level tag memory and in said device-level tag memory, and is not so loaded otherwise; and wherein said split transaction bus system includes a tag pipeline bypass such that state transactions on said address bus occur atomically, logically, without dependence upon a response thereto.
Claim 18
Dependent Claim
46 words
The split transaction bus system protocol of claim 1, wherein each packet of address data is two clock cycles long, each packet of transaction data is two clock cycles long, and address bus and data bus arbitration on said arbitration bus alternate with each clock cycle.
Claim 19
Dependent Claim
27 words
The split transaction bus system protocol of claim 1, wherein latency between an asserted transaction request and a response thereto is as small as two clock cycles.
Claim 20
Dependent Claim
33 words
The split transaction bus system protocol of claim 1, wherein said device includes at least one device selected from the group consisting of (i) a central processor unit, and (ii) an input/output unit.
Claim 21
Dependent Claim
39 words
The split transaction bus system protocol of claim 1, wherein said system includes a data bus and a single arbitration bus that is time-multiplexed for arbitrating access to said address bus and for arbitrating access to said data bus.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-06-07 | 2002-12-07 | 2003-06-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-06-07 | 2006-12-07 | 2007-06-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-06-07 | 2010-12-07 | 2011-06-08 | $7700.00 | Window Closed / Lapsed |