Arbitration of packet switched busses, including busses for shared memory multiprocessors

Claim 1

An arbiter for resolving bus contention in a system having a synchronous packet switched bus, and a plurality of client devices that are interfaced with said bus; said client devices being synchronously clocked at a predetermined frequency for synchronously exchanging packets of information via said bus on a contention basis; each of said packets having a duration spanning a plurality of consecutive clock cycles on said bus, such that each packet has an initial cycle and a final cycle; said arbiter comprising: a plurality of ports, each of said client devices being coupled to a respective one of said ports for registering arbitration requests with said arbiter and for receiving corresponding bus grants from said arbiter; said arbitration requests having a plurality of permissible encodings that said arbiter recognizes as representing requests for bus grants of differing durations, with at least some of said client devices having provision for registering arbitration requests with said arbiter for grants of different predetermined lengths to acquire control of said bus for packets spanning different numbers of clock cycles on said bus; and logic coupled to said ports for arbitrating said arbitration requests, in advance of each of said bus grants, in accordance with predetermined arbitration rules to provide bus grants spanning an appropriate number of clock cycles on said bus in response to one after another of said arbitration requests; each of said bus grants being time limited to give the client device to which a particular grant is communicated exclusive control of said bus for the duration of a single packet, with said control commencing and terminating concurrently with the initial cycle and the final cycle, respectively, of said packet; said arbitration requests being arbitrated sufficiently in advance of each of said bus grants based on control information provided by said logic that enables the client devices to anticipate and discriminate between bus grants for said different request types to enable said client devices to pack packets into consecutive clock cycles on said bus.