US5909658A
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High speed electron beam lithography pattern processing system
Assignee: GlobalFoundries Inc
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Filing: 1996-06-18
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Granted: 1999-06-01
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Expires: 2016-06-18
Abstract
Abstract A pattern data processor system is disclosed that comprises a pattern storage device for storing pattern data, a Redundant Array of Independent Disks (RAID) pattern memory buffer for receiving and temporarily holding the pattern data from the pattern storage device, a shape processor for processing and decoding the pattern data, a shape divider, and a shape generator for generating a shape from the decoded pattern data. The shape processor comprises a programmable gate array device (FPGA) that dynamically decodes different pattern data formats with different decoding schemes, allowing for high speed processing. A Previous Output Shape (POS) Register is also disclosed, which uses information from previous shapes to decompress new shapes, thus allowing for variable length macro and pattern data, and conserving disk space.
Inventors
- 👤 Eileen Veronica Clarke
- 👤 John William Kay
- 👤 Christine Ann Kostek
- 👤 Jon Erik Lieberman
- 👤 Daniel Lee Pierce
- 👤 Robert Joseph Quickle
- 👤 John Matthew Safran
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 12:19
CPC Classifications
H; H01; H01J; H01J37/00; H01J37/30; H01J37/302; H01J2237/00; H01J2237/30; H01J2237/317; H01J2237/3175; H01J2237/31761; H01J2237/31762
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
125 words
A pattern data processing system, comprising: a pattern storage device for storing pattern data and configuration data, said pattern data having a plurality of encoding schemes and said configuration data having a plurality of decoding schemes corresponding to said encoding schemes; a pattern memory buffer, coupled to said pattern storage device, for receiving and holding said pattern data from said pattern storage device; a dynamically reconfigurable programmable array device, coupled to said pattern memory buffer, for dynamically decoding said pattern data having a plurality of encoding schemes with said plurality of decoding schemes, wherein said configuration data reconfigures said dynamically reconfigurable programmable array device; and a shape generator, coupled to said dynamically reconfigurable programmable array device, for generating a shape from said decoded pattern data.
Claim 2
Dependent Claim
125 words
A pattern data processing system, comprising: a pattern storage device for storing pattern data and configuration data, said pattern data having a plurality of encoding schemes and said configuration data having a plurality of decoding schemes corresponding to said encoding schemes; a pattern memory buffer, coupled to said pattern storage device, for receiving and holding said pattern data from said pattern storage device; a dynamically reconfigurable programmable array device, coupled to said pattern memory buffer, for dynamically decoding said pattern data having a plurality of encoding schemes with said plurality of decoding schemes, wherein said configuration data reconfigures said dynamically reconfigurable programmable array device; and a shape generator, coupled to said dynamically reconfigurable programmable array device, for generating a shape from said decoded pattern data.
Claim 3
Dependent Claim
20 words
The system of claim 1, wherein said pattern memory buffer is a Redundant Array of Independent Disks (RAID) memory buffer.
Claim 4
Dependent Claim
54 words
The system of claim 1, wherein said dynamically reconfigurable programmable array device further comprises: a register for referencing a present shape pattern data element to a prior shape pattern data element, wherein said pattern memory buffer stores only the variation between said present shape pattern data element and said prior shape pattern data element.
Claim 5
Dependent Claim
15 words
The system of claim 3, wherein said register is a Previous Output Shape (POS) register.
Claim 6
Dependent Claim
35 words
The system of claim 1, wherein said dynamically reconfigurable programmable array device further comprises: a direct memory access (DMA) bus master for providing DMA operations independent of a processor from said pattern data processing system.
Claim 7
Dependent Claim
21 words
The system of claim 5, wherein said DMA bus master is a Versa Module Eurocard Subsystem Bus (VSB) DMA bus master.
Claim 8
Independent Claim
121 words
A method for generating a pattern with a pattern data processing system comprising the steps of: a) storing pattern data and configuration data into a memory buffer, said pattern data having a first and a second encoding scheme and said configuration data having a plurality of decoding schemes corresponding to said encoding schemes; b) decoding said pattern data having said first encoding scheme with a first decoding scheme, and decoding said pattern data having said second encoding scheme with a second decoding scheme, wherein said second encoding scheme is decoded within the same job as said first encoding scheme; c) reconfiguring a dynamically reconfigurable programmable array device utilizing said configuration data; and d) generating a shape from said decoded pattern data.
Claim 9
Independent Claim
121 words
A method for generating a pattern with a pattern data processing system comprising the steps of: a) storing pattern data and configuration data into a memory buffer, said pattern data having a first and a second encoding scheme and said configuration data having a plurality of decoding schemes corresponding to said encoding schemes; b) decoding said pattern data having said first encoding scheme with a first decoding scheme, and decoding said pattern data having said second encoding scheme with a second decoding scheme, wherein said second encoding scheme is decoded within the same job as said first encoding scheme; c) reconfiguring a dynamically reconfigurable programmable array device utilizing said configuration data; and d) generating a shape from said decoded pattern data.
Claim 10
Dependent Claim
46 words
The method of claim 7, further comprising the step of: referencing a present shape pattern data element to a prior shape pattern data element, wherein said memory buffer stores only the variation between said present shape pattern data element and said prior shape pattern data element.
Claim 11
Dependent Claim
16 words
The method of claim 8, wherein said referencing step uses a Previous Output Shape (POS) register.
Claim 12
Dependent Claim
33 words
The method of claim 7, further comprising the step of: transferring said pattern data through direct memory accessing (DMA), wherein said DMA is independent of a processor from said pattern data processing system.
Claim 13
Dependent Claim
15 words
The method of claim 10, wherein a VSB DMA bus master performs said DMA operations.
Claim 14
Dependent Claim
20 words
The method of claim 7, wherein said pattern memory buffer is a Redundant Array of Independent Disks (RAID) memory buffer.
Claim 15
Dependent Claim
132 words
A lithography system having a pattern processor subsystem, said system comprising: a pattern storage device for supplying pattern data and configuration data, said pattern data having a plurality of encoding schemes and said configuration data having a plurality of decoding schemes corresponding to said plurality of encoding schemes; a pattern memory buffer, coupled to said pattern storage device, for receiving and holding said pattern data from said pattern storage device; a dynamically reconfigurable programmable array device, coupled to said pattern memory buffer, for dynamically decoding said pattern data having a plurality of encoding schemes with said plurality of decoding schemes, wherein said configuration data reconfigures said dynamically reconfigurable programmable array device; and a shape generator, coupled to said dynamically reconfigurable programmable array device, for generating a shape from said decoded pattern data.
Claim 16
Dependent Claim
132 words
A lithography system having a pattern processor subsystem, said system comprising: a pattern storage device for supplying pattern data and configuration data, said pattern data having a plurality of encoding schemes and said configuration data having a plurality of decoding schemes corresponding to said plurality of encoding schemes; a pattern memory buffer, coupled to said pattern storage device, for receiving and holding said pattern data from said pattern storage device; a dynamically reconfigurable programmable array device, coupled to said pattern memory buffer, for dynamically decoding said pattern data having a plurality of encoding schemes with said plurality of decoding schemes, wherein said configuration data reconfigures said dynamically reconfigurable programmable array device; and a shape generator, coupled to said dynamically reconfigurable programmable array device, for generating a shape from said decoded pattern data.
Claim 17
Dependent Claim
20 words
The system of claim 13, wherein said pattern memory buffer is a Redundant Array of Independent Disks (RAID) memory buffer.
Claim 18
Dependent Claim
54 words
The system of claim 13, wherein said dynamically reconfigurable programmable array device further comprises: a register for referencing a present shape pattern data element to a prior shape pattern data element, wherein said pattern memory buffer stores only the variation between said present shape pattern data element and said prior shape pattern data element.
Claim 19
Dependent Claim
15 words
The system of claim 15, wherein said register is a Previous Output Shape (POS) register.
Claim 20
Dependent Claim
34 words
The system of claim 13, wherein said dynamically reconfigurable programmable array device further comprises: a direct memory access (DMA) bus master for providing DMA operations independent of a processor from said pattern processor subsystem.
Claim 21
Dependent Claim
21 words
The system of claim 17, wherein said DMA bus master is a Versa Module Eurocard Subsystem Bus (VSB) DMA bus master.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-05-31 | 2002-11-30 | 2003-06-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-05-31 | 2006-11-30 | 2007-06-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-05-31 | 2010-11-30 | 2011-06-01 | $7700.00 | Window Closed / Lapsed |