Patent JPS5968833A successfully refreshed from Google Patents.
Patent US5909619A successfully refreshed from Google Patents.
US5909619A
Expired / Lapsed
US
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Method for forming a DRAM cell and array to store two-bit data
Assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Filing: 1998-02-04
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Granted: 1999-06-01
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Expires: 2018-02-04
Abstract
Abstract A DRAM cell capable of storing two bits of digital data as four levels of stored charge within the DRAM cell is disclosed. The four level DRAM cell has a pass transistor, a trench capacitor, and a stack capacitor. The pass transistors has a source connected to a bit line voltage generator to control placement of the charge within the four level DRAM cell, a gate connected to a word line voltage generator to control activation of the DRAM cells, and a drain. The trench capacitor has a top plate connected to the drain and a bottom plate connected to a substrate biasing voltage source. The stack capacitor has a first plate connected to the drain and a second plate connected to a coupling-gate voltage generator. The coupling-gate voltage generator will provide four levels of voltage that will indicate the level of charge to be stored within the four level DRAM cell. An interconnecting block that will interconnect the top plate of the trench capacitor to the first plate of the stack capacitor. The interconnection point between the trench capacitor and the stack capacitor will form the storage node that will retain the level of charge that indicates the state of the two bits of digital data. Four level DRAM cells will be arranged in a plurality of rows and columns to form an array of four level DRAM cells.
Inventors
- 👤 Min-Hwa Chi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 04:33
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/56; G11C11/565; H; H10; H10B; H10B12/00
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
347 words
A method of fabrication of a plurality of four level DRAM cells whereby each four level DRAM cell has a pass transistor, a trench capacitor coupled to the pass transistor, and a stack capacitor coupled to the pass transistor and the trench capacitor so as to retain two bits of digital data, wherein said method comprises the steps of: a) providing a semiconductor substrate having a surface implanted with a material of a first conductivity type; b) creating a deep well by implanting a material of a second conductivity type into said surface of said semiconductor substrate; c) creating a shallow well by implanting the material of the first conductivity type into said deep well; d) creating the pass transistor in the semiconductor substrate by: creating the source and drain by the material of the second conductivity type into said shallow well at a channel distance apart, growing a gate oxide on the surface of said semiconductor substrate in the area between the source and the drain, and creating the gate by depositing a depositing a first conductive material above the gate oxide; e) forming the trench capacitor in the semiconductor substrate by: etching a trench into the surface of the semiconductor substrate such that the semiconductor substrate is the bottom plate of said trench capacitor, depositing a trench dielectric on an inner surface of said trench, and filling said trench with a first polysilicon material to form the top plate of said trench capacitor. f) forming an interconnecting block by depositing a second polysilicon material on the drain and top plate to connect said drain to said top plate; g) forming an insulating layer is formed by depositing a first insulating material on the surface of the semiconductor substrate; h) forming the stack capacitor by: depositing a third polysilicon layer upon said insulating layer and said interconnecting block to form a first plate; depositing a second insulating material upon said first plate to form a capacitor dielectric for said stack capacitor; and depositing a fourth polysilicon layer upon said capacitor dielectric to form a second plate.
Claim 2
Independent Claim
347 words
A method of fabrication of a plurality of four level DRAM cells whereby each four level DRAM cell has a pass transistor, a trench capacitor coupled to the pass transistor, and a stack capacitor coupled to the pass transistor and the trench capacitor so as to retain two bits of digital data, wherein said method comprises the steps of: a) providing a semiconductor substrate having a surface implanted with a material of a first conductivity type; b) creating a deep well by implanting a material of a second conductivity type into said surface of said semiconductor substrate; c) creating a shallow well by implanting the material of the first conductivity type into said deep well; d) creating the pass transistor in the semiconductor substrate by: creating the source and drain by the material of the second conductivity type into said shallow well at a channel distance apart, growing a gate oxide on the surface of said semiconductor substrate in the area between the source and the drain, and creating the gate by depositing a depositing a first conductive material above the gate oxide; e) forming the trench capacitor in the semiconductor substrate by: etching a trench into the surface of the semiconductor substrate such that the semiconductor substrate is the bottom plate of said trench capacitor, depositing a trench dielectric on an inner surface of said trench, and filling said trench with a first polysilicon material to form the top plate of said trench capacitor. f) forming an interconnecting block by depositing a second polysilicon material on the drain and top plate to connect said drain to said top plate; g) forming an insulating layer is formed by depositing a first insulating material on the surface of the semiconductor substrate; h) forming the stack capacitor by: depositing a third polysilicon layer upon said insulating layer and said interconnecting block to form a first plate; depositing a second insulating material upon said first plate to form a capacitor dielectric for said stack capacitor; and depositing a fourth polysilicon layer upon said capacitor dielectric to form a second plate.
Claim 3
Dependent Claim
23 words
The method of claim 1 wherein the first conductive material is selected from the group of conductive materials consisting of polysilicon and tungsten.
Claim 4
Dependent Claim
17 words
The method of claim 1 wherein the semiconductor substrate is connected to the substrate biasing voltage source.
Claim 5
Dependent Claim
27 words
The method of claim 1 wherein the gate of the pass transistor is connected to a word line voltage generator to activate and deactivate said pass transistor.
Claim 6
Dependent Claim
39 words
The method of claim 1 wherein the source of the pass transistor is connected to a bit line voltage generator to establish a necessary bit line voltage level during a writing and reading of said four level DRAM cells.
Claim 7
Dependent Claim
38 words
The method of claim 1 wherein the second plate of the stack capacitor is connected to a coupling-gate voltage generator to establish a necessary coupling-gate voltage level during the writing and reading of said four level DRAM cells.
Claim 8
Dependent Claim
110 words
The method of claim 1 wherein if the two bits of digital data are to be written as both being at a first logic level, the word line voltage generator will be boosted to a level greater than a power supply voltage source to activate said pass transistor, the bit line voltage generator will be set to a level approximately on half the power supply voltage source, the coupling-gate voltage generator will be set to a level approximately that of the power supply voltage source, and the substrate biasing voltage source will be set to a level that is the negative of one half of the power supply voltage source.
Claim 9
Dependent Claim
134 words
The method of claim 1 wherein if the first of the two bits of digital data is to be written as being at a second logic level and the second of the two bits of digital data is to be written at the first logic level, the word line voltage generator will be boosted to a level greater than a power supply voltage source to activate said pass transistor, the bit line voltage generator will be set to a level approximately on half the power supply voltage source, the coupling-gate voltage generator will be set to a level approximately that of one half of the power supply voltage source, and the substrate biasing voltage source will be set to a level that is the negative of one half of the power supply voltage source.
Claim 10
Dependent Claim
130 words
The method of claim 1 wherein if the first of the two bits of digital data is to be written as being at the first logic level and the second of the two bits of digital data is to be written at a second logic level, the word line voltage generator will be boosted to a level greater than a power supply voltage source to activate said pass transistor, the bit line voltage generator will be set to a level approximately on half the power supply voltage source, the coupling-gate voltage generator will be set to a level approximately that of the ground reference potential, and the substrate biasing voltage source will be set to a level that is the negative of one half of the power supply voltage source.
Claim 11
Dependent Claim
116 words
The method of claim 1 wherein if the two bits of digital data is to be written as being at the second logic level, the word line voltage generator will be boosted to a level greater than a power supply voltage source to activate said pass transistor, the bit line voltage generator will be set to a level approximately on half the power supply voltage source, the coupling-gate voltage generator will be set to a level approximately that is the negative of one half that of the power supply voltage source, and the substrate biasing voltage source will be set to a level that is the negative of one half of the power supply voltage source.
Claim 12
Dependent Claim
38 words
The method of claim 1 wherein a four level charge sense amplifier is connected to said bit line to sense a level of charge representing the two bits of digital data retained within said four level DRAM cell.
Claim 13
Dependent Claim
103 words
The method of claim 11 wherein said four level DRAM cell is read by setting the word line voltage generator will be boosted to a level greater than a power supply voltage source to activate said pass transistor, the bit line voltage generator will be set to a level approximately on half the power supply voltage source to precharge said bit line, the coupling-gate voltage generator will be set to a level that is the ground reference potential, and the substrate biasing voltage source will be set to a level that is the negative of one half of the power supply voltage source.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-05-31 | 2002-11-30 | 2003-06-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-05-31 | 2006-11-30 | 2007-06-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-05-31 | 2010-11-30 | 2011-06-01 | $7700.00 | Window Closed / Lapsed |