Method of forming a polycide gate of a semiconductor device

Claim 1

A method for forming a polycide gate of a semiconductor device, comprising the steps of: (a) providing a semiconductor substrate having applied thereon in spatial succession, an oxide film layer, a polysilicon layer, a metal silicide layer and a patterned etching mask layer covering less than all of said metal silicide layer, so that a respective uncovered portion of the metal silicide layer is available for etching from an outer surface thereof, one interface exists where said metal silicide layer adjoins the polysilicon layer, and another interface exists where said polysilicon layer adjoins the oxide film layer; (b) applying a plasma by transfer plasma coupling equipment at a transfer coupling plasma power level in the range of from 250 to about 350 watts inwards through a gap of 5.9 cm towards said substrate, where the metal silicide layer is not covered by said etching mask layer while subjecting particles in the plasma to bottom electrode power at a first power level in the range of from 200 to about 300 watts, for increasing the energy with which the plasma particles collide with each other to a first energy level, for thereby etching away layer material, including all of the metal silicide layer where not covered by said etching mask layer, inwards to a level which is at least as close to said substrate as said one interface, leaving in place on said oxide film layer a remainder of said polysilicon layer not covered by said etching mask layer; and (c) applying a plasma by said transfer plasma coupling equipment at a transfer coupling plasma power level in the range of from 250 to about 350 watts inwards through a gap of 5.9 cm towards said substrate while subjecting particles in the plasma to bottom electrode power at a second power level in the range of from 70 to about 130 watts, for increasing the energy with which the plasma particles collide with each other to a second level which is lower than said first energy level, where said remainder of said polysilicon layer is not covered by said etching mask layer, and thereby etching away said remainder of said polysilicon layer where not covered by said etching mask layer.

Claim 2

A method for forming a polycide gate of a semiconductor device, comprising the steps of: (a) providing a semiconductor substrate having applied thereon in spatial succession, an oxide film layer, a polysilicon layer, a metal silicide layer and a patterned etching mask layer covering less than all of said metal silicide layer, so that a respective uncovered portion of the metal silicide layer is available for etching from an outer surface thereof, one interface exists where said metal silicide layer adjoins the polysilicon layer, and another interface exists where said polysilicon layer adjoins the oxide film layer; (b) applying a plasma by transfer plasma coupling equipment at a transfer coupling plasma power level in the range of from 250 to about 350 watts inwards through a gap of 5.9 cm towards said substrate, where the metal silicide layer is not covered by said etching mask layer while subjecting particles in the plasma to bottom electrode power at a first power level in the range of from 200 to about 300 watts, for increasing the energy with which the plasma particles collide with each other to a first energy level, for thereby etching away layer material, including all of the metal silicide layer where not covered by said etching mask layer, inwards to a level which is at least as close to said substrate as said one interface, leaving in place on said oxide film layer a remainder of said polysilicon layer not covered by said etching mask layer; and (c) applying a plasma by said transfer plasma coupling equipment at a transfer coupling plasma power level in the range of from 250 to about 350 watts inwards through a gap of 5.9 cm towards said substrate while subjecting particles in the plasma to bottom electrode power at a second power level in the range of from 70 to about 130 watts, for increasing the energy with which the plasma particles collide with each other to a second level which is lower than said first energy level, where said remainder of said polysilicon layer is not covered by said etching mask layer, and thereby etching away said remainder of said polysilicon layer where not covered by said etching mask layer.