US5529197A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Polysilicon/polycide etch process for sub-micron gate stacks
Assignee: Qimonda AG
•
Filing: 1994-12-20
•
Granted: 1996-06-25
•
Expires: 2014-12-20
Abstract
Abstract A method for fabricating a stacked gate array on a semiconductor wafer. The method comprises the steps of providing a reaction chamber having an upper inductive coil and a lower capacitive electrode. The upper inductive coil is adjusted to a relatively low power setting of substantially less than 300 watts. The wafer is placed into the reaction chamber and plasma etched to provide the stacked gate array.
Inventors
- 👤 Virinder S. Grewal
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 16:40
CPC Classifications
H; H01; H01J; H01J37/00; H01J37/32; H01J37/32009; H01J37/32082; H01J37/321; H10; H10P; H10P50/00; H10P50/20; H10P50/26; H10P50/264; H10P50/266; H10P50/267; H10P50/268; H01J2237/00; H01J2237/32; H01J2237/33; H01J2237/334; H01J2237/3343; H01J2237/3348
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
63 words
A method for fabricating a stacked gate array on a semiconductor wafer, comprising the steps of: providing a reaction chamber having an upper inductive means and a lower capacitive means; adjusting said upper inductive means to a power setting of substantially less than 300 watts; placing said wafer into said reaction chamber; and plasma etching said wafer to provide said stacked gate array.
Claim 2
Independent Claim
63 words
A method for fabricating a stacked gate array on a semiconductor wafer, comprising the steps of: providing a reaction chamber having an upper inductive means and a lower capacitive means; adjusting said upper inductive means to a power setting of substantially less than 300 watts; placing said wafer into said reaction chamber; and plasma etching said wafer to provide said stacked gate array.
Claim 3
Dependent Claim
22 words
The method according to claim 1, wherein said stacked gate array comprises a layer of n-doped polysilicon and a layer of oxide.
Claim 4
Dependent Claim
26 words
The method according to claim 1, wherein said stacked gate array comprises a layer of polysilicon, a layer of tungsten silicon and a layer of oxide.
Claim 5
Dependent Claim
26 words
The method according to claim 1, wherein said stacked gate array comprises a layer of polysilicon, a layer of titanium silicon and a layer of oxide.
Claim 6
Dependent Claim
48 words
The method according to claim 1, wherein said step of plasma etching comprises the steps of: feeding at least one etching gas into said reaction chamber; and energizing said inductive and capacitive means to convert said at least one etching gas into a plasma to etch said wafer.
Claim 7
Dependent Claim
21 words
The method according to claim 5, further comprising the step of evacuating said reaction chamber before said step of plasma etching.
Claim 8
Dependent Claim
17 words
The method according to claim 5, wherein said at least one etching gas comprises four etching gases.
Claim 9
Dependent Claim
15 words
The method according to claim 7, wherein one of said four etching gases comprises HCL.
Claim 10
Dependent Claim
17 words
The method according to claim 7, wherein one of said four etching gases comprises CL 2 .
Claim 11
Dependent Claim
17 words
The method according to claim 7, wherein one of said four etching gases comprises N 2 .
Claim 12
Dependent Claim
17 words
The method according to claim 7, wherein one of said four etching gases comprises O 2 .
Claim 13
Dependent Claim
23 words
The method according to claim 1, wherein said power of said upper inductive means is adjusted to between about 0 and 200 watts.
Claim 14
Dependent Claim
23 words
The method according to claim 1, wherein said power of said lower capacitive means is adjusted to between about 50 and 200 watts.
Claim 15
Dependent Claim
26 words
The method according to claim 1, further comprising the step of adjusting said lower capacitive means to a power setting of substantially less than 300 watts.
Claim 16
Dependent Claim
40 words
The method according to claim 14, wherein said power of said upper inductive means is adjusted to between about 0 and 200 watts and said power of said lower capacitive means is adjusted to between about 50 and 200 watts.
Claim 17
Independent Claim
77 words
A method for fabricating a sub-micron gate stack comprised of a plurality of layers on a semiconductor wafer, said method comprising the steps of: providing a reaction chamber having an upper inductive coil and a lower capacitive electrode; adjusting said upper inductive coil to a power setting of about 0 to 200 watts; placing said wafer into said reaction chamber; evacuating said reaction chamber; and etching said wafer with a plasma to provide said stacked gate array.
Claim 18
Independent Claim
77 words
A method for fabricating a sub-micron gate stack comprised of a plurality of layers on a semiconductor wafer, said method comprising the steps of: providing a reaction chamber having an upper inductive coil and a lower capacitive electrode; adjusting said upper inductive coil to a power setting of about 0 to 200 watts; placing said wafer into said reaction chamber; evacuating said reaction chamber; and etching said wafer with a plasma to provide said stacked gate array.
Claim 19
Dependent Claim
43 words
The method according to claim 16, wherein said step of etching comprises the steps of: feeding a plurality etching gases into said reaction chamber; and energizing said coil and said electrode to convert said etching gases into said plasma to etch said wafer.
Claim 20
Dependent Claim
21 words
The method according to claim 16, wherein said etching gases comprises HCL, CL 2 , N 2 and O 2 .
Claim 21
Dependent Claim
26 words
The method according to claim 16, wherein said power of said lower capacitive electrode is adjusted to a power setting of between 50 and 200 watts.
Claim 22
Independent Claim
107 words
A method for fabricating a sub-micron gate stack on a semiconductor wafer, said method comprising the steps of: forming a polysilicon layer on said wafer; forming an oxide layer over said polysilicon layer; placing said wafer into a reaction chamber having an upper inductive coil and a lower capacitive electrode; adjusting said upper inductive coil to a power setting of substantially less than 300 watts; evacuating said reaction chamber; and feeding a plurality etching gases into said reaction chamber; and energizing said coil and said electrode to convert said etching gases into a plasma to etch said layers of said wafer to form said sub-micron gate stack.
Claim 23
Independent Claim
107 words
A method for fabricating a sub-micron gate stack on a semiconductor wafer, said method comprising the steps of: forming a polysilicon layer on said wafer; forming an oxide layer over said polysilicon layer; placing said wafer into a reaction chamber having an upper inductive coil and a lower capacitive electrode; adjusting said upper inductive coil to a power setting of substantially less than 300 watts; evacuating said reaction chamber; and feeding a plurality etching gases into said reaction chamber; and energizing said coil and said electrode to convert said etching gases into a plasma to etch said layers of said wafer to form said sub-micron gate stack.
References Cited (Backward Citations)
US4561907A
Cited
US4659426A
Cited
US4785337A
Cited
US5106776A
Cited
US5202275A
Cited
US5275972A
Cited
US5212116A
Cited
US5022958A
Cited
US5126916A
Cited
US5227325A
Cited
US5286344A
Cited
US5405480A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-06-25 | 1999-12-25 | 2000-06-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-06-25 | 2003-12-25 | 2004-06-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-06-25 | 2007-12-25 | 2008-06-25 | $7700.00 | Window Closed / Lapsed |