US5106776A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of making high performance composed pillar dRAM cell
Assignee: Texas Instruments Inc
•
Filing: 1991-05-15
•
Granted: 1992-04-21
•
Expires: 2011-05-15
Abstract
Abstract A dRAM memory cell structure and a method for forming the same is disclosed. Each memory cell is formed at a pillar, where the storage plate is an inversion region created by a field plate surrounding all sides of each pillar and separated therefrom by a storage dielectric film. The field plate is formed in a grid shape, and is disposed at the bottom of the trenches surrounding the array of pillars to serve as the fixed plate for all storage capacitors in the array. At the top of each pillar is a diffusion to which the bit lines are connected. Disposed in the trench above the field plate and extending in one direction are word lines. Each word line is formed of a polysilicon filament onto which tungsten is deposited by way of selective CVD. The word line is formed closely adjacent the pillars in its associated row, separated therefrom by a gate dielectric film, the word line is separated from the adjacent row by a dielectric film which is thicker than the gate dielectric, so that the word line will cause conduction between the inversion region and the top diffusion for its associated row, but not for the adjacent row.
Inventors
- 👤 Bing W. Shen
- 👤 William F. Richardson
- 👤 Robert R. Doering
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 21:18
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/30; H10B12/39; H10B12/395; H10B12/01; H10B12/02; H10B12/03; H10B12/038; H10B12/0383
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
216 words
A method of forming a memory array at a surface of a semiconductor body of a first conductivity type, comprising: etching a trench grid at selected locations of said surface to leave a plurality of pillars arranged in rows and columns; forming an isolation structure at the bottom of said trench grid; forming a storage dielectric on the sides of said pillars; forming a field plate grid disposed over said isolation structure and separated from said pillars by said storage dielectric; forming a gate dielectric on a side of each pillar in a first row of pillars; forming a thick dielectric on a side of each pillar in a second row of pillars, said second row of pillars being adjacent said first row of pillars on the side of said gate dielectric; forming a word line for said first row of pillars disposed over said field plate grid and between the gate dielectric for the pillars in said first row and the thick dielectric for the pillars in said second row; forming a diffusion at the tops of said pillars in said first row; and forming a bit line for with each column of pillars, each said bit line contacting the diffusion at the top of the pillar in said first row associated with its column.
Claim 2
Independent Claim
216 words
A method of forming a memory array at a surface of a semiconductor body of a first conductivity type, comprising: etching a trench grid at selected locations of said surface to leave a plurality of pillars arranged in rows and columns; forming an isolation structure at the bottom of said trench grid; forming a storage dielectric on the sides of said pillars; forming a field plate grid disposed over said isolation structure and separated from said pillars by said storage dielectric; forming a gate dielectric on a side of each pillar in a first row of pillars; forming a thick dielectric on a side of each pillar in a second row of pillars, said second row of pillars being adjacent said first row of pillars on the side of said gate dielectric; forming a word line for said first row of pillars disposed over said field plate grid and between the gate dielectric for the pillars in said first row and the thick dielectric for the pillars in said second row; forming a diffusion at the tops of said pillars in said first row; and forming a bit line for with each column of pillars, each said bit line contacting the diffusion at the top of the pillar in said first row associated with its column.
Claim 3
Dependent Claim
45 words
The method of claim 1, wherein said step of forming said isolation structures comprises: forming a layer comprising silicon nitride over said sidewalls of said pillars; exposing the bottom of said trench grid; and growing an oxide layer at the bottom of said trench grid.
Claim 4
Dependent Claim
35 words
The method of claim 2, wherein said step of forming said isolation structures further comprises: etching a hollowed portion at the bottom of said trench grid prior to said step of growing an oxide layer.
Claim 5
Dependent Claim
94 words
The method of claim 1, wherein said steps of forming said gate dielectric and forming said thick dielectric comprise: forming a dielectric layer filling said trench grid over said field plate; and etching a selected portion of said dielectric layer lying between said first row and said second row to remove said dielectric layer near said first row of pillars, leaving said thick dielectric on the sides of said second row of pillars; and growing a gate oxide layer on the first row of pillars in the location where said dielectric layer was etched.
Claim 6
Dependent Claim
40 words
The method of claim 4, wherein said step of forming said word line comprises: forming a polysilicon line disposed between said gate oxide layer on said first row of pillars and said thick dielectric on said second row of pillars.
Claim 7
Dependent Claim
47 words
The method of claim 5, wherein said step of forming said word line further comprises: anisotropically etching said polysilicon line to leave a polysilicon filament adjacent said gate oxide layer on said first row of pillars; and depositing a metal layer in contact with said polysilicon filament.
Claim 8
Dependent Claim
20 words
The method of claim 6, wherein said step of depositing a metal layer comprises selective chemical vapor deposition of tungsten.
Claim 9
Dependent Claim
77 words
The method of claim 1, wherein said steps of forming said gate dielectric and forming said thick dielectric comprise: forming a gate oxide layer on the sides of said pillars over over said field plate; filling the trenches between said pillars with polysilicon; etching a selected portion of said polysilicon to leave a portion thereof lying between said first row and said second row; and filling the locations where said polysilicon was etched with a dielectric material.
References Cited (Backward Citations)
US4672410A
Cited
JPS6173366A
Cited
EP0198590A2
Cited
US4751558A
Cited
US4830978A
Cited
US5008214A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-04-21 | 1995-10-21 | 1996-04-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-04-21 | 1999-10-21 | 2000-04-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-04-21 | 2003-10-21 | 2004-04-21 | $7700.00 | Window Closed / Lapsed |