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US5903489A
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Semiconductor memory device having a monitoring pattern
Assignee: NEC Corp
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Filing: 1998-09-18
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Granted: 1999-05-11
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Expires: 2018-09-18
Abstract
Abstract A semiconductor memory device has a memory cell area and a peripheral area including a scribe area. A large number of first monitoring patterns are disposed in the scribe area for monitoring the peripheral circuit in the peripheral area, whereas a few number of second monitoring patterns are disposed adjacent to the memory cell area for monitoring the characteristics of the memory cells. A CMP process which reduces the thickness of the memory device does not generate dust of the conductive material from the scribe area because the first monitoring pattern has a level substantially equal to the level of the peripheral area.
Inventors
- 👤 Kiminori Hayano
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 14:42
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/01; H10B12/30; H10B12/50; H10D; H10D89/00; H10D89/10
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
94 words
A semiconductor memory device comprising a memory cell area including a plurality of memory cells, a peripheral area including a peripheral circuit for controlling said memory cells, said peripheral area including a scribe area at an outer periphery thereof, a first monitoring pattern disposed in said scribe area, said first monitoring pattern having a level substantially equal to a level of said peripheral circuit, and a second monitoring pattern disposed in an area other than said scribe area, said second monitoring pattern having a level substantially equal to a level of said memory cells.
Claim 2
Dependent Claim
94 words
A semiconductor memory device comprising a memory cell area including a plurality of memory cells, a peripheral area including a peripheral circuit for controlling said memory cells, said peripheral area including a scribe area at an outer periphery thereof, a first monitoring pattern disposed in said scribe area, said first monitoring pattern having a level substantially equal to a level of said peripheral circuit, and a second monitoring pattern disposed in an area other than said scribe area, said second monitoring pattern having a level substantially equal to a level of said memory cells.
Claim 3
Dependent Claim
24 words
A semiconductor memory device as defined in claim 1, wherein said second monitoring pattern has a structure for monitoring characteristics of said memory cell.
Claim 4
Dependent Claim
24 words
A semiconductor memory device as defined in claim 1, wherein said first monitoring pattern has a structure for monitoring characteristics of said peripheral area.
Claim 5
Dependent Claim
22 words
A semiconductor memory device as defined in claim 1, wherein said second monitoring pattern is disposed adjacent to said memory cell area.
Claim 6
Dependent Claim
41 words
A semiconductor memory device as defined in claim 1, wherein said memory cell area includes a plurality of memory blocks each including an array of memory cells, and said second monitoring pattern is disposed in a space between said memory blocks.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-05-10 | 2002-11-09 | 2003-05-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-05-10 | 2006-11-09 | 2007-05-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-05-10 | 2010-11-09 | 2011-05-11 | $7700.00 | Window Closed / Lapsed |