Abstract A semiconductor memory device reduces the distance occupied between a data path circuit and pads, and minimizes the length of data lines and main input/output lines, thereby improving an operating speed thereof. The semiconductor memory device includes a memory array divided into four array blocks which are independently arranged; a plurality of pads disposed in an area between the upper array blocks and the respective lower array blocks; a data path control circuit disposed in an area between the left array blocks and the respective right array blocks; a data path circuit disposed in a middle center area among the four array blocks; a plurality of data lines connecting the pads to the data path circuit; and a plurality of main input/output lines connecting the memory array to the data path circuit. In this configuration, a distance between the data lines and the main input/output lines and the data path circuit can be minimized.
A semiconductor memory device, comprising: a memory array having four spaced apart and discrete array blocks, including a first array block located in an upper left quadrant of said memory array, a second array block located in a lower left quadrant of said memory array, a third array block located in an upper right quadrant of said memory array, and a fourth array block located in a lower right quadrant of said memory array; a plurality of pads disposed in at least one of a first middle area extending between said first and third array blocks and a second middle area extending between said second and fourth array blocks; a data pad control circuit disposed in at least one of a first center area extending between said first and third array blocks and a second center area extending between said second and fourth array blocks; a data path circuit disposed in a middle center area of said memory array, said middle center area extending between the first and second middle areas and between the first and second center areas; a plurality of data lines connecting said pads to said data path circuitry; and a plurality of main input/output lines connecting said memory array to said data path circuit.
Claim 2
Dependent Claim
208 words
A semiconductor memory device, comprising: a memory array having four spaced apart and discrete array blocks, including a first array block located in an upper left quadrant of said memory array, a second array block located in a lower left quadrant of said memory array, a third array block located in an upper right quadrant of said memory array, and a fourth array block located in a lower right quadrant of said memory array; a plurality of pads disposed in at least one of a first middle area extending between said first and third array blocks and a second middle area extending between said second and fourth array blocks; a data pad control circuit disposed in at least one of a first center area extending between said first and third array blocks and a second center area extending between said second and fourth array blocks; a data path circuit disposed in a middle center area of said memory array, said middle center area extending between the first and second middle areas and between the first and second center areas; a plurality of data lines connecting said pads to said data path circuitry; and a plurality of main input/output lines connecting said memory array to said data path circuit.
Claim 3
Dependent Claim
24 words
The semiconductor memory device as claimed in claim 1, further comprising power lines and bus lines which are located in said middle center area.
Claim 4
Dependent Claim
30 words
The semiconductor memory device as claimed in claim 2, wherein said power lines and said bus lines are disposed in a different layer than that of said data path circuit.