Method for forming field effect transistor having multiple gate electrodes surrounding the channel region

Claim 1

A method of forming a field effect transistor, comprising the steps of: fabricating a protrusion on a semiconductor substrate; forming a thin insulation film on the semiconductor substrate having the protrusion formed thereon; forming a film of an electrode material on said thin insulation film and then forming a gate electrode pattern to at least three surfaces on the side walls of said protrusion by etching; forming source and drain regions on both ends of said protrusion; forming an oxide film on said protrusion and said gate electrode and then planarizing said oxide film; appending another substrate to said planarized oxide film; removing said semiconductor substrate, thereby exposing said thin insulation film and a surface of the protrusion; and further forming an oxide film and a gate electrode on the surface of the protrusion.

Claim 2

A method of forming a field effect transistor, comprising the steps of: fabricating a protrusion on a semiconductor substrate; forming a thin insulation film on the semiconductor substrate having the protrusion formed thereon; forming a film of an electrode material on said thin insulation film and then forming a gate electrode pattern to at least three surfaces on the side walls of said protrusion by etching; forming source and drain regions on both ends of said protrusion; forming an oxide film on said protrusion and said gate electrode and then planarizing said oxide film; appending another substrate to said planarized oxide film; removing said semiconductor substrate, thereby exposing said thin insulation film and a surface of the protrusion; and further forming an oxide film and a gate electrode on the surface of the protrusion.

Claim 3

A method of forming a field effect transistor, comprising the steps of; forming a first impurity region in a semiconductor substrate; removing the surface of said substrate, thereby exposing the surface of said impurity region; forming a pattern comprising a semiconductor layer on said impurity region, thereby defining a channel region; forming a thin insulation film on the surface of the pattern of said semiconductor layer; growing an electrode material layer on said insulation film; patterning said electrode material layer, thereby forming a gate electrode pattern at the periphery of said semiconductor layer; etching back said gate electrode pattern until said thin insulation film is exposed; forming a second impurity region to said channel region on the side opposed to said first impurity region; forming the first and the second impurity regions as source and drain regions and removing said exposed thin insulation film, thereby exposing the electrode material formed as a channel region; and removing the gate electrode pattern formed to the periphery of said semiconductor layer at a portion in contact with the second impurity layer directly or by way of the thin insulation film.

Claim 4

A method of forming a field effect transistor, comprising the steps of; forming a first impurity region in a semiconductor substrate; removing the surface of said substrate, thereby exposing the surface of said impurity region; forming a pattern comprising a semiconductor layer on said impurity region, thereby defining a channel region; forming a thin insulation film on the surface of the pattern of said semiconductor layer; growing an electrode material layer on said insulation film; patterning said electrode material layer, thereby forming a gate electrode pattern at the periphery of said semiconductor layer; etching back said gate electrode pattern until said thin insulation film is exposed; forming a second impurity region to said channel region on the side opposed to said first impurity region; forming the first and the second impurity regions as source and drain regions and removing said exposed thin insulation film, thereby exposing the electrode material formed as a channel region; and removing the gate electrode pattern formed to the periphery of said semiconductor layer at a portion in contact with the second impurity layer directly or by way of the thin insulation film.