Method for fabricating a capped gate conductor

Claim 1

A process for fabricating a gate structure in a CMOS which comprises: forming device regions in a semiconductor substrate; forming an N well region and a P-type well region in said semiconductor substrate by ion implantation or diffusion; forming a gate isolation layer over active regions as defined by the isolation regions; providing a gate forming polycrystalline silicon layer above said gate isolation layer; providing the gate forming polycrystalline silicon layer doping; depositing a sacrificial gate cap over said gate forming polycrystalline silicon layer wherein said sacrificial gate cap is etchable at a faster rate than the dielectric interlayer to be subsequently formed; etching said sacrificial gate cap and said gate forming polycrystalline silicon material layer to thereby define individual gate channel regions and polycrystalline gate; forming source and drain regions by ion implantation or diffusion; forming sacrificial-spacer on the vertical sides of the sacrificial gate cap and polycrystalline gate; depositing interlayer dielectric material to a depth at least equal to the combined height of the polycrystalline gate and sacrificial gate cap; planarizing said interlayer dielectric material; at least partially removing said etched sacrificial gate cap after planarizing said interlayer dielectric material; at least partially removing said sacrificial spacer after removing said etched sacrificial gate cap; depositing a self-aligned metallic gate conductor above said polycrystalline silicon gate, selectively etching a top portion of said gate conductor to form a trench; and depositing a cap dielectric wherein said cap dielectric is etchable at a slower rate than said interlayer dielectric.