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US5897327A
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Method of evaluating a semiconductor wafer
Assignee: Sumco Techxiv Corp
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Filing: 1998-01-27
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Granted: 1999-04-27
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Expires: 2018-01-27
Abstract
Abstract A MOS capacitor in which an insulating layer of thermal oxide film is disposed between the electrode 2 and the silicon wafer 1 is formed. While a light beam of an energy larger than 1.1 eV is irradiated on the electrode 2 and its periphery, electrons inject from the electrode 2 side (voltage is applied from the silicon wafer 1 side). The injected electrons are activated by the light irradiation. For both p-type or n-type semiconductor, the dielectric breakdown electric field strength can be precisely measured according to the degree of processing defects. The evaluation method is particularly effective for the n-type semiconductor wafer, which was difficult to evaluate by the prior art.
Inventors
- 👤 Eiichi Asano
- 👤 Hisami Motoura
- 👤 Yasuhiro Shimada
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 03:12
CPC Classifications
H; H10; H10P; H10P74/00; H10P74/20; H10P74/203
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
50 words
A method of evaluating a semiconductor wafer, comprising: forming an oxide film and electrode on the semiconductor wafer; and measuring an I-V characteristic between the semiconductor wafer and the electrode by impinging electrons from electrodes and applying voltage to the substrate while irradiating the electrode and periphery thereof with light.
Claim 2
Independent Claim
50 words
A method of evaluating a semiconductor wafer, comprising: forming an oxide film and electrode on the semiconductor wafer; and measuring an I-V characteristic between the semiconductor wafer and the electrode by impinging electrons from electrodes and applying voltage to the substrate while irradiating the electrode and periphery thereof with light.
Claim 3
Dependent Claim
26 words
The method of evaluating a semiconductor wafer as claimed in claim 1, wherein the irradiation energy is larger than 1.1 eV in the step of measuring.
Claim 4
Dependent Claim
23 words
The method of evaluating a semiconductor wafer as claimed in claim 1, wherein the semiconductor wafer to be evaluated is a processed wafer.
Claim 5
Dependent Claim
24 words
The method of evaluating a semiconductor wafer as claimed in claim 3, wherein the semiconductor wafer to be evaluated is a mirror polished wafer.
Claim 6
Dependent Claim
24 words
The method of evaluating a semiconductor wafer as claimed in claim 1, wherein the semiconductor wafer to be evaluated is a p-type silicon wafer.
Claim 7
Dependent Claim
24 words
The method of evaluating a semiconductor wafer as claimed in claim 1, wherein the semiconductor wafer to be evaluated is a n-type silicon wafer.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-04-26 | 2002-10-26 | 2003-04-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-04-26 | 2006-10-26 | 2007-04-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-04-26 | 2010-10-26 | 2011-04-27 | $7700.00 | Window Closed / Lapsed |