Patent US5893732A successfully refreshed from Google Patents.
US5893732A
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Method of fabricating intermediate SRAM array product and conditioning memory elements thereof
Assignee: Micron Technology Inc
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Filing: 1998-03-11
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Granted: 1999-04-13
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Expires: 2018-03-11
Abstract
Abstract An intermediate semiconductor product in a semiconductor fabrication process. The intermediate semiconductor product comprises an array of memory cells on a semiconductor substrate, where each cell includes an access device having an active semiconductor region and a memory element positioned in ohmic contact with the active semiconductor region. The intermediate semiconductor product further comprises a first wiring commonly connected to the memory element of each memory cell; and a second wiring commonly connected to the active semiconductor region of each memory cell, whereby, upon application of a voltage across the first and second wirings, conditioning current may flow in parallel through the memory elements to concurrently condition a programmable memory characteristic of the memory elements. A fabricating method is also provided. The method comprises the steps of forming an array of devices on a substrate, each device including first and second components, the first component having a first side and a second side electrically connected in series circuit with the second component at a node; applying a first wiring over the cells in electrical circuit connection with the first sides of the first components; applying a second wiring over the cells in electrical circuit connection with the nodes; and applying a voltage across the first and second wirings to produce parallel conditioning current flows through the first components and bypassing the second components; and removing the second wiring.
Inventors
- 👤 Donald M. Morgan
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 11:13
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10B; H10B63/00; H10B63/10
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
109 words
A semiconductor fabricating method comprising the steps of: forming an array of cells on a substrate, each cell including first and a second components, the first component having a first side and a second side electrically connected in series circuit with the second component at a node; applying a first wiring over the cells in electrical circuit connection with the first sides of the first components; applying a second wiring over the cells in electrical circuit connection with the nodes; applying a voltage across the first and second wirings to produce parallel conditioning current flows through the first components and bypassing the second components; and removing the second wiring.
Claim 2
Dependent Claim
109 words
A semiconductor fabricating method comprising the steps of: forming an array of cells on a substrate, each cell including first and a second components, the first component having a first side and a second side electrically connected in series circuit with the second component at a node; applying a first wiring over the cells in electrical circuit connection with the first sides of the first components; applying a second wiring over the cells in electrical circuit connection with the nodes; applying a voltage across the first and second wirings to produce parallel conditioning current flows through the first components and bypassing the second components; and removing the second wiring.
Claim 3
Dependent Claim
24 words
The fabricating method of claim 1, further including the step of forming the nodes in the substrate as active regions for the second components.
Claim 4
Dependent Claim
25 words
The fabricating method defined in claim 2, wherein the device array forming step includes the step of forming the first components as chalcogenide memory elements.
Claim 5
Dependent Claim
25 words
The fabricating method defined in claim 3, wherein the device array forming step further includes the step of forming the second components as MOS transistors.
Claim 6
Independent Claim
262 words
A method of fabricating a Random Access Memory (RAM), comprising the steps of: forming an array of doped surface regions in a semiconductor substrate to serve as active regions for memory cell access devices; depositing a first oxide layer over a surface of the substrate including surfaces of the active regions; selectively etching the first oxide layer to create first contact windows exposing a first portion of the active region surfaces; depositing a layer of memory element material over a surface of the first oxide layer and into the first contact windows; removing the memory element material layer from the first oxide layer surface to create discrete memory elements in the first contact windows in ohmic contact with the first surface portions of the active regions; forming a second oxide layer over the first oxide layer and the discrete memory elements; selectively etching the first and second oxide layers to create plural pairs of second and third contact windows, the second contact windows exposing the memory elements and the third contact windows exposing second portions of the active region surfaces; depositing a conductive material layer over a surface of the second oxide layer and into the second and third contact windows; patterning the conductive material layer on said surface of the second oxide layer to create first and second wirings, said first wiring electrically connecting with the memory elements, and said second wiring electrically connecting with the active region second surface portions; and applying a voltage across the first and second wirings to produce parallel conditioning current flows through the memory elements.
Claim 7
Independent Claim
262 words
A method of fabricating a Random Access Memory (RAM), comprising the steps of: forming an array of doped surface regions in a semiconductor substrate to serve as active regions for memory cell access devices; depositing a first oxide layer over a surface of the substrate including surfaces of the active regions; selectively etching the first oxide layer to create first contact windows exposing a first portion of the active region surfaces; depositing a layer of memory element material over a surface of the first oxide layer and into the first contact windows; removing the memory element material layer from the first oxide layer surface to create discrete memory elements in the first contact windows in ohmic contact with the first surface portions of the active regions; forming a second oxide layer over the first oxide layer and the discrete memory elements; selectively etching the first and second oxide layers to create plural pairs of second and third contact windows, the second contact windows exposing the memory elements and the third contact windows exposing second portions of the active region surfaces; depositing a conductive material layer over a surface of the second oxide layer and into the second and third contact windows; patterning the conductive material layer on said surface of the second oxide layer to create first and second wirings, said first wiring electrically connecting with the memory elements, and said second wiring electrically connecting with the active region second surface portions; and applying a voltage across the first and second wirings to produce parallel conditioning current flows through the memory elements.
Claim 8
Dependent Claim
14 words
The method of claim 5, further including the step of removing the second wiring.
Claim 9
Dependent Claim
16 words
The method of claim 5, further including the step of removing the first and second wirings.
Claim 10
Dependent Claim
22 words
The method of claim 7, further including the step of depositing a third metal wiring in electrical connections with the memory elements.
Claim 11
Dependent Claim
13 words
The method of claim 5, wherein the memory element material is a chalcogenide.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-04-12 | 2002-10-12 | 2003-04-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-04-12 | 2006-10-12 | 2007-04-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-04-12 | 2010-10-12 | 2011-04-13 | $7700.00 | Window Closed / Lapsed |