Method for making stacked and borderless via structures for multilevel metal interconnections on semiconductor substrates

Claim 1

A method for making stacked and borderless via structures for multilevel metal interconnections for integrated circuits on semiconductor substrates comprising the steps of: a) providing a semiconductor substrate having semiconductor devices formed in and on said substrate and having a patterned first conducting layer formed thereon; b) depositing an intermetal dielectric layer over said patterned first conducting layer and planarizing said intermetal dielectric layer; c) depositing a hard mask layer on said intermetal dielectric layer; d) patterning said hard mask layer and partially etching into said intermetal dielectric layer and forming trenches for a patterned second conducting layer using a first photoresist mask and a first anisotropic plasma etching; e) forming a second photoresist mask having openings extending over portions of said trenches and using a second anisotropic plasma etch to remove said intermetal dielectric layer remaining in said openings to said patterned first conducting layer while said exposed hard mask serves as an etch stop layer, thereby forming vias in said intermetal dielectric layer self-aligned to and in said trenches; f) depositing a conformal second conducting layer and filling said vias and said trenches; g) chemically-mechanically polishing back said second conformal conducting layer to said intermetal dielectric layer and further overpolishing to remove any residue of said second conducting layer remaining in recesses formed in said hard mask layer resulting during said second anisotropic etching, thereby forming borderless via structures and forming a patterned conducting layer in said trenches coplanar with said intermetal dielectric layer; h) repeating steps b) through g) for each additional level of metal interconnections as required to complete said integrated circuits, and further forming stacked vias, as needed, to reduce said integrated circuit area.

Claim 2

A method for making stacked and borderless via structures for multilevel metal interconnections for integrated circuits on semiconductor substrates comprising the steps of: a) providing a semiconductor substrate having semiconductor devices formed in and on said substrate and having a patterned first conducting layer formed thereon; b) depositing an intermetal dielectric layer over said patterned first conducting layer and planarizing said intermetal dielectric layer; c) depositing a hard mask layer on said intermetal dielectric layer; d) patterning said hard mask layer and partially etching into said intermetal dielectric layer and forming trenches for a patterned second conducting layer using a first photoresist mask and a first anisotropic plasma etching; e) forming a second photoresist mask having openings extending over portions of said trenches and using a second anisotropic plasma etch to remove said intermetal dielectric layer remaining in said openings to said patterned first conducting layer while said exposed hard mask serves as an etch stop layer, thereby forming vias in said intermetal dielectric layer self-aligned to and in said trenches; f) depositing a conformal second conducting layer and filling said vias and said trenches; g) chemically-mechanically polishing back said second conformal conducting layer to said intermetal dielectric layer and further overpolishing to remove any residue of said second conducting layer remaining in recesses formed in said hard mask layer resulting during said second anisotropic etching, thereby forming borderless via structures and forming a patterned conducting layer in said trenches coplanar with said intermetal dielectric layer; h) repeating steps b) through g) for each additional level of metal interconnections as required to complete said integrated circuits, and further forming stacked vias, as needed, to reduce said integrated circuit area.

Claim 12

A method for making stacked and borderless via structures for multilevel metal interconnections for integrated circuits on semiconductor substrates comprising the steps of: a) providing a semiconductor substrate having semiconductor devices formed in and on said substrate and having a patterned first conducting layer composed of a conductively doped polysilicon layer formed thereon; b) depositing an intermetal dielectric layer composed of silicon oxide over said patterned first conducting layer and planarizing said intermetal dielectric layer; c) depositing a hard mask layer composed of silicon nitride on said intermetal dielectric layer; d) patterning said hard mask layer and partially etching into said intermetal dielectric layer and forming trenches for a patterned second conducting layer using a first photoresist mask and a first anisotropic plasma etching; e) forming a second photoresist mask having openings extending over portions of said trenches and using a second anisotropic plasma etch to remove said intermetal dielectric layer remaining in said openings to said patterned first conducting layer while said exposed hard mask serves as an etch stop layer, thereby forming vias in said intermetal dielectric layer self-aligned to and in said trenches; f) depositing a conformal second conducting layer, composed of a metal layer, and filling said vias and said trenches; g) chemically-mechanically polishing back said second conducting layer to said intermetal dielectric layer and further overpolishing to remove any residue of said second conducting layer remaining in recesses formed in said hard mask layer resulting during said second anisotropic etching, thereby forming borderless via structures and forming a patterned conducting layer in said trenches coplanar with said intermetal dielectric layer; h) repeating steps b) through g) for each additional level of metal interconnections as required to complete said integrated circuits, and further forming stacked vias, as needed, to reduce said integrated circuit.

Claim 13

A method for making stacked and borderless via structures for multilevel metal interconnections for integrated circuits on semiconductor substrates comprising the steps of: a) providing a semiconductor substrate having semiconductor devices formed in and on said substrate and having a patterned first conducting layer composed of a conductively doped polysilicon layer formed thereon; b) depositing an intermetal dielectric layer composed of silicon oxide over said patterned first conducting layer and planarizing said intermetal dielectric layer; c) depositing a hard mask layer composed of silicon nitride on said intermetal dielectric layer; d) patterning said hard mask layer and partially etching into said intermetal dielectric layer and forming trenches for a patterned second conducting layer using a first photoresist mask and a first anisotropic plasma etching; e) forming a second photoresist mask having openings extending over portions of said trenches and using a second anisotropic plasma etch to remove said intermetal dielectric layer remaining in said openings to said patterned first conducting layer while said exposed hard mask serves as an etch stop layer, thereby forming vias in said intermetal dielectric layer self-aligned to and in said trenches; f) depositing a conformal second conducting layer, composed of a metal layer, and filling said vias and said trenches; g) chemically-mechanically polishing back said second conducting layer to said intermetal dielectric layer and further overpolishing to remove any residue of said second conducting layer remaining in recesses formed in said hard mask layer resulting during said second anisotropic etching, thereby forming borderless via structures and forming a patterned conducting layer in said trenches coplanar with said intermetal dielectric layer; h) repeating steps b) through g) for each additional level of metal interconnections as required to complete said integrated circuits, and further forming stacked vias, as needed, to reduce said integrated circuit.