← Back to Patent Explorer
US5189506A Expired / Lapsed US ⏱️ 0.0 years remaining

Triple self-aligned metallurgy for semiconductor devices

Assignee: International Business Machines Corp
•
Filing: 1992-06-03
•
Granted: 1993-02-23
•
Expires: 2012-06-03
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract A process is described which eliminates the need to account for mask alignment tolerances in forming vias for metallurgy by the use of a common vertical edge or common plane defined by a first mask representing a first level of interconnect. Subsequent masks for defining interconnecting vias and a second level of interconnect utilize at least one edge of the first mask pattern as a common element to define subsequent metal levels. The combination of an etch stop layer and an oversized second level mask enable the mask overlay to be eliminated.

Inventors

  • 👤 John E. Cronin
  • 👤 Carter W. Kaanta

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-01 21:07
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/063; H10W20/056; H10W20/058; H10W20/069; H10W20/0693

Claims Analysis

Total Claims: 4
Claim 1
Independent Claim 70 words
A metallurgical structure for an integrated circuit having a conductive member formed in a recess in a layer of insulating material by sequential first, second and third mask-definable layers of conductive material characterized in that each of said layers of conductive material has a substantially vertical surface portion adjacent to said insulating material and terminating in at least one common plane defined in said insulating material by said first mask.
Claim 2
Dependent Claim 70 words
A metallurgical structure for an integrated circuit having a conductive member formed in a recess in a layer of insulating material by sequential first, second and third mask-definable layers of conductive material characterized in that each of said layers of conductive material has a substantially vertical surface portion adjacent to said insulating material and terminating in at least one common plane defined in said insulating material by said first mask.
Claim 3
Dependent Claim 36 words
The structure of claim 1 wherein the first mask-definable layer represents a first metallurgical interconnection layer, the second mask-definable layer represents a stud interconnection layer and the third mask-definable layer represents a second metallurgical interconnection layer.
Claim 4
Dependent Claim 20 words
The structure of claim 1 wherein said common plane is formed by a dielectric layer defined by a first mask.

References Cited (Backward Citations)

US4582563A Cited
US4789648A Cited
US4892843A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1996-02-23 1996-08-24 1997-02-23 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2000-02-23 2000-08-24 2001-02-23 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2004-02-23 2004-08-24 2005-02-23 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag